High speed vision processor with reconfigurable processing element array based on full-custom distributed memory

2016 ◽  
Vol 55 (4S) ◽  
pp. 04EF08
Author(s):  
Zhe Chen ◽  
Jie Yang ◽  
Cong Shi ◽  
Qi Qin ◽  
Liyuan Liu ◽  
...  
Keyword(s):  
High Speed ◽  
Distributed Memory ◽  
Processing Element ◽  
Reconfigurable Processing ◽  
Element Array

Amorphous Silicon Ultra Thin Base Bipolar Phototransistor with High Performance (β=12, τx ≤30μs)

1985 ◽  
Vol 54 ◽  
Author(s):  
C. Y. Chang ◽  
B. S. Wu ◽  
Y. K. Fang ◽  
R. H. Lee
Keyword(s):  
Amorphous Silicon ◽  
High Speed ◽  
High Performance ◽  
Response Speed ◽  
High Gain ◽  
Bipolar Transistor ◽  
Current Gain ◽  
Flat Panel Display ◽  
Element Array ◽  
Good Agreement

ABSTRACTAn n+ /i/p /i/n amorphous silicon bipolar transistor has been successfully fabricated with a current gain of 12 and a response speed of 30 yS This new structure of bipolar transistor has a very thin base (200Å), therefore, high gain and high speed is obtainable. This device has a very promising applications as a flat panel display transistor and a phototransistor in photosensing element/array and photo coupler. Electrical and optical characteristics have been extensively investigated. Theoretical model and experimental results are plausibly in good agreement.Variation from the fundamental structure is also been developed, such as the Schottky emitter Al/i/p /i/n bipolar transistor.

scholarly journals LEVERAGING SHARED CACHES FOR PARALLEL TEMPORAL BLOCKING OF STENCIL CODES ON MULTICORE PROCESSORS AND CLUSTERS

2010 ◽  
Vol 20 (04) ◽  
pp. 359-376 ◽  
Author(s):  
MARKUS WITTMANN ◽  
GEORG HAGER ◽  
JAN TREIBIG ◽  
GERHARD WELLEIN
Keyword(s):  
High Speed ◽  
Distributed Memory ◽  
Multicore Processors ◽  
Memory Bandwidth ◽  
Performance Models ◽  
Shared Caches ◽  
Strong Scaling ◽  
Stencil Codes ◽  
Multicore Chips ◽  
Synthetic Modeling

Bandwidth-starved multicore chips have become ubiquitous. It is well known that the performance of stencil codes can be improved by temporal blocking, lessening the pressure on the memory interface. We introduce a new pipelined approach that makes explicit use of shared caches in multicore environments and minimizes synchronization and boundary overhead. Benchmark results are presented for three current x86-based microprocessors, showing clearly that our optimization works best on designs with high-speed shared caches and low memory bandwidth per core. We furthermore demonstrate that simple bandwidth-based performance models are inaccurate for this kind of algorithm and employ a more elaborate, synthetic modeling procedure. Finally we show that temporal blocking can be employed successfully in a hybrid shared/distributed-memory environment, albeit with limited benefit at strong scaling.

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