Amorphous Silicon Ultra Thin Base Bipolar Phototransistor with High Performance (β=12, τx ≤30μs)

1985 ◽  
Vol 54 ◽  
Author(s):  
C. Y. Chang ◽  
B. S. Wu ◽  
Y. K. Fang ◽  
R. H. Lee
Keyword(s):  
Amorphous Silicon ◽  
High Speed ◽  
High Performance ◽  
Response Speed ◽  
High Gain ◽  
Bipolar Transistor ◽  
Current Gain ◽  
Flat Panel Display ◽  
Element Array ◽  
Good Agreement

ABSTRACTAn n+ /i/p /i/n amorphous silicon bipolar transistor has been successfully fabricated with a current gain of 12 and a response speed of 30 yS This new structure of bipolar transistor has a very thin base (200Å), therefore, high gain and high speed is obtainable. This device has a very promising applications as a flat panel display transistor and a phototransistor in photosensing element/array and photo coupler. Electrical and optical characteristics have been extensively investigated. Theoretical model and experimental results are plausibly in good agreement.Variation from the fundamental structure is also been developed, such as the Schottky emitter Al/i/p /i/n bipolar transistor.

scholarly journals Ultra-high speed reconfigurable microwave and radio frequency photonic intensity differentiators using Kerr frequency optical microcombs

2021 ◽  
Author(s):  
David Moss
Keyword(s):  
Radio Frequency ◽  
High Speed ◽  
High Performance ◽  
Third Order ◽  
Transversal Filter ◽  
Multi Wavelength ◽  
Gaussian Input ◽  
On Chip ◽  
The Cost ◽  
Good Agreement

Abstract We propose and experimentally demonstrate a microwave photonic intensity differentiator based on a Kerr optical comb generated by a compact integrated micro-ring resonator (MRR). The on-chip Kerr optical comb, containing a large number of comb lines, serves as a high-performance multi-wavelength source for the transversal filter, which will greatly reduce the cost, size, and complexity of the system. Moreover, owing to the compactness of the integrated MRR, up to 200-GHz frequency spacing of the Kerr optical comb can be achieved, enabling a potential operation bandwidth of over 100 GHz. By programming and shaping individual comb lines according to the calculated tap weights, a reconfigurable intensity differentiator with variable differentiation orders can be realized. The operation principle is theoretically analyzed, and experimental demonstrations of first-order, second-order, and third-order differentiation functions based on the principle are presented. The radio frequency (RF) amplitude and phase responses of multi-order intensity differentiations are characterized, and system demonstrations of real-time differentiations for Gaussian input signal are also performed. The experimental results show good agreement with theory, confirming the effectiveness of our approach.

1600 V, 5.1 mΩ●cm2 4H-SiC BJT with a High Current Gain of β=70

2008 ◽  
Vol 600-603 ◽  
pp. 1155-1158 ◽  
Author(s):  
Jian Hui Zhang ◽  
Petre Alexandrov ◽  
Jian Hui Zhao
Keyword(s):  
High Performance ◽  
Voltage Drop ◽  
High Gain ◽  
Current Gain ◽  
High Current ◽  
Large Area ◽  
Collector Current ◽  
Forward Voltage Drop ◽  
Ac Current ◽  
Dc Current

This paper reports a newly achieved best result on the common emitter current gain of 4H-SiC high power bipolar junction transistors (BJTs). A fabricated 1600 V – 15 A 4H-SiC power BJT with an active area of 1.7 mm2 shows a high DC current gain (b) of 70, when it conducts 9.8 A collector current at a base current of only 140 mA. The maximum AC current gain (DIC/DIB) is up to 78. This high performance BJT has an open base collector-to-emitter blocking voltage (VCEO) of over 1674 V with a leakage current of 1.6 μA, and a specific on-resistance (RSP-ON) of 5.1 mW.cm2 when it conducts 7.0 A (412 A/cm2) at a forward voltage drop of VCE = 2.1 V. A large area 4H-SiC BJT with a footprint of 4.1 mm x 4.1 mm has also shown a DC current gain over 50. These high-gain, high-voltage and high-current 4H-SiC BJTs further support a promising future for 4H-SiC BJT applications.

A High-Performance Sigma-Delta Modulator in 0.18μm CMOS Technology

2014 ◽  
Vol 519-520 ◽  
pp. 1085-1088
Author(s):  
Ying Qi Qian ◽  
Chang Chun Zhang ◽  
Zhong Chao Liu ◽  
Lei Lei Liu ◽  
Yu Rong Luan ◽  
...  
Keyword(s):  
Radio Frequency Identification ◽  
High Speed ◽  
High Performance ◽  
Dynamic Range ◽  
Low Voltage ◽  
Intermediate Frequency ◽  
Cmos Technology ◽  
High Gain ◽  
Sigma Delta Modulator ◽  
Sigma Delta

Sigma-Delta (∑∆) modulators are commonly used in high-resolution analog-to-digital converters (ADCs). In this paper, a high-performance modulator targeted for ultra-high-frequency (UHF) radio-frequency identification (RFID) zero-intermediate frequency (ZIF) receivers is designed in standard 0.18μm CMOS technology. The modulator has been designed with switched-capacitor (SC) integrators employing gain-boosted operational amplifiers, voltage comparators and nonoverlapping clock generators to satisfy such requirements as high gain, low voltage and wide bandwidth. The behavioral-level modeling and circuit-level design are carried out with MATLAB/Simulink and Cadence/SpectreRF, respectively. Ultimately, the high-speed and low-power realization of a second-order single-bit modulator with an oversampling ratio (OSR) of 32 is presented. Simulation results shown that, from a 1.8V supply, operated at a sampling frequency of 64MHz, a dynamic range of 53.4dB over a signal bandwidth of 1MHz is achieved.

scholarly journals Direct Numerical Simulation and Visualization of Subcooled Pool Boiling

2014 ◽  
Vol 2014 ◽  
pp. 1-11 ◽  
Author(s):  
Tomoaki Kunugi ◽  
Yasuo Ose
Keyword(s):  
Numerical Simulation ◽  
Direct Numerical Simulation ◽  
High Speed ◽  
High Performance ◽  
High Spatial Resolution ◽  
Pool Boiling ◽  
Numerical Results ◽  
Condensation Model ◽  
High Performance Computers ◽  
Good Agreement

A direct numerical simulation of the boiling phenomena is one of the promising approaches in order to clarify their heat transfer characteristics and discuss the mechanism. During these decades, many DNS procedures have been developed according to the recent high performance computers and computational technologies. In this paper, the state of the art of direct numerical simulation of the pool boiling phenomena during mostly two decades is briefly summarized at first, and then the nonempirical boiling and condensation model proposed by the authors is introduced into the MARS (MultiInterface Advection and Reconstruction Solver developed by the authors). On the other hand, in order to clarify the boiling bubble behaviors under the subcooled conditions, the subcooled pool boiling experiments are also performed by using a high speed and high spatial resolution camera with a highly magnified telescope. Resulting from the numerical simulations of the subcooled pool boiling phenomena, the numerical results obtained by the MARS are validated by being compared to the experimental ones and the existing analytical solutions. The numerical results regarding the time evolution of the boiling bubble departure process under the subcooled conditions show a very good agreement with the experimental results. In conclusion, it can be said that the proposed nonempirical boiling and condensation model combined with the MARS has been validated.

Micro Crystalline Silicon TFT by the Metal Capped Diode Laser Thermal Annealing Method

2008 ◽  
Vol 1066 ◽  
Author(s):  
Toshiaki Arai ◽  
Narihiro Morosawa ◽  
Yoshio Inagaki ◽  
Koichi Tatsuki ◽  
Tetsuo Urabe
Keyword(s):  
Amorphous Silicon ◽  
Thermal Annealing ◽  
Threshold Voltage ◽  
High Performance ◽  
Crystalline Silicon ◽  
Stress Test ◽  
Flat Panel Display ◽  
Flat Panel ◽  
Large Size ◽  
Annealing Method

ABSTRACTA novel crystallization method for silicon based thin film transistor (TFT) is proposed for the fabrication of high performance large size flat panel displays. In spite of using almost the same TFT fabrication process as that of hydrogenated amorphous silicon (a-Si:H) TFT, the proposed metal capped laser thermal annealing method realizes the formation of uniform and dense micro crystalline silicon (μc-Si), and provides mobility of 3.1 cm2/V•s, threshold voltage (ΔVth) of 2.3 V, and sub threshold slope (S) of 0.93 V/decade. Moreover, proposed stacked n+ amorphous silicon structure realizes extremely low off-current maintaining high on-current. As the reliability of TFT, a threshold voltage sift (ΔVth) under the high current bias stress test (BTS) condition was investigated, and realized the assumed ΔVth of +1.77 V after 100,000 hours stress of 10 μA and 50°C. This value is 2 orders smaller than that of a-Si:H TFT and only three times larger than that of low temperature poly silicon (LTPS) TFT.We believe that our μc-Si TFT technology is the suitable solution for the high quality, large size flat panel display mass-production.

AlGaAs/GaAs HBTs FOR ANALOG AND DIGITAL APPLICATIONS

1994 ◽  
Vol 05 (03) ◽  
pp. 213-252 ◽  
Author(s):  
KEH-CHUNG WANG ◽  
RANDALL B. NUBLING ◽  
KEN PEDROTTI ◽  
NENG-HAUNG SHENG ◽  
PETER M. ASBECK ◽  
...  
Keyword(s):  
High Speed ◽  
High Performance ◽  
High Accuracy ◽  
Bipolar Transistor ◽  
Heterojunction Bipolar Transistor ◽  
Electronic Systems ◽  
Ic Technology

AlGaAs/GaAs Heterojunction Bipolar Transistor (HBT) technology has emerged as an important IC technology for high performance electronic systems. Many outstanding circuits have been demonstrated as a result of the AlGaAs/GaAs HBTs high speed, high accuracy and its semi-insulating substrate. Several GaAs HBT manufacturing lines have been established; some of which are shipping products. In this paper, we describe AlGaAs/GaAs HBT technology, summarize some key and representative circuits in analog, A/D conversion and digital applications, and provide prospects of GaAs HBT research.

The Role of the Si-SiO2 (CVD) Interface in Degradation Effects for High-Speed Bipolar Transistors

1995 ◽  
Vol 378 ◽  
Author(s):  
J.-Q. Lü ◽  
S. Schöttl ◽  
E. Stefanov ◽  
F. Koch ◽  
R. Mahnkopf ◽  
...  
Keyword(s):  
High Speed ◽  
Tunneling Current ◽  
Bipolar Transistors ◽  
Bipolar Transistor ◽  
Current Gain ◽  
Current Increase ◽  
Base Current ◽  
2D Simulation ◽  
Trap Assisted Tunneling ◽  
Emitter Junction

AbstractThe intent of the present work is to analyze device degradation and reliability in terms of their microscopic origins. The base-emitter junction of the advanced, “double-poly”, self-aligned bipolar transistor contacts the SiO2 sidewall spacer. During normal circuit operation, the base-emitter junction experiences a reverse bias which as a stress in time degrades the current gain of the transistor. Both a decrease of the gain, as well as an increase in the noise are observed. The forward base current increase as a function of stress time follows △IB ∼ tn. We present evidence that the defects are occurring at the Si-Si02 interface from perimeter to area comparisons. The weak temperature dependence of the forward base current in degraded transistors shows that trap-assisted tunneling current through the Si-SiO2 interface states is involved. The random-telegraph-signals observed for the first time in a silicon bipolar transistor are a direct identification of damage at the Si-SiO2 interface. 2D simulation of the potential and field near the interface allows us to show that damage can be expected.

High Performance Input Scanning Arrays Using Amorphous Silicon Photodiodesand Thin-Film Transistors

1992 ◽  
Vol 258 ◽  
Author(s):  
Richard L. Weisfield
Keyword(s):  
Thin Film ◽  
Amorphous Silicon ◽  
Thin Film Transistors ◽  
High Speed ◽  
High Performance ◽  
Test Results ◽  
Large Area ◽  
Full Page ◽  
Hydrogenated Amorphous ◽  
Low Capacitance

ABSTRACTThe use of large area hydrogenated amorphous silicon (a-Si:H) technology has enabled compact, full page width scanners to be built inexpensively, and is now the dominant method for fabricating low-end facsimile machines. This technology has now been extended to scanners with considerably higher levels of performance. High speed, high resolution, full-width input scanning arrays have been developed using a-Si:H photodiodes and thin-film transistors (TFTs). A 12” long array has been designed to scan 3 colors at 400 spots per inch, and operates at speeds of up to 40 pages per minute, achieving a signal/noise ratio of 400:1 at intensities of 30 μWcm-2.The color scan array is made using 3 rows of a-Si:H photodiodes, one per color, addressed by TFTs which share sets of common data lines. The data lines are arranged in a low capacitance non-crossing configuration which allows the scanner to achieve high responsivity with low crosstalk. The data lines are connected to a number of readout chips, each of which amplifies and multiplexes the photosignals onto a single video output line. Optoelectronic test results and images obtained from this device will be presented. These results indicate that high quality color images can be obtained from a-Si:H scanners, and that the present scanner is more limited by the speed of the readout chips than by the a-Si: H devices themselves.

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