PMOS Thin-Film Transistors Fabricated in RTCVD Polycrystalline Silicon Germanium Films

1995 ◽  
Author(s):  
Seo-Kyu Lee ◽  
Hyung-Geun Kim ◽  
Wook-Jin Chung ◽  
B. K. Kang ◽  
Ohyun Kim
Keyword(s):  
Thin Film ◽  
Silicon Germanium ◽  
Thin Film Transistors ◽  
Polycrystalline Silicon ◽  
Germanium Films

Polycrystalline silicon-germanium thin-film transistors

1994 ◽  
Vol 41 (9) ◽  
pp. 1581-1591 ◽  
Author(s):  
Tsu-Jae King ◽  
K.C. Saraswat
Keyword(s):  
Thin Film ◽  
Silicon Germanium ◽  
Thin Film Transistors ◽  
Polycrystalline Silicon

Low Thermal Budget Polycrystalline Silicon-Germanium Thin-Film Transistors Fabricated by Rapid Thermal Annealing

1994 ◽  
Vol 33 (Part 2, No. 8B) ◽  
pp. L1139-L1141 ◽  
Author(s):  
Steve Jurichich ◽  
Tsu-Jae King ◽  
Krishna Saraswat ◽  
John Mehlhaff
Keyword(s):  
Thin Film ◽  
Thermal Annealing ◽  
Rapid Thermal Annealing ◽  
Silicon Germanium ◽  
Thin Film Transistors ◽  
Polycrystalline Silicon ◽  
Thermal Budget ◽  
Low Thermal Budget

Evidence For Heterojunction Effects in Polycrystalline Si1-xGex Thin Film Transistors With Si Caps

1998 ◽  
Vol 533 ◽  
Author(s):  
Albert W. Wang ◽  
Krishna C. Saraswat
Keyword(s):  
Thin Film ◽  
Silicon Germanium ◽  
Thin Film Transistors ◽  
Polycrystalline Silicon ◽  
Gate Dielectric ◽  
Inversion Layer ◽  
Flat Panel Displays ◽  
Strained Si ◽  
Effective Medium Model ◽  
High Temperature Processes

AbstractPolycrystalline silicon-germanium (poly-Si1-xGex) thin film transistors (TFTs) werefabricated with and without Si interlayers (caps) to buffer the SiO2 gate dielectric and theSi1-xGex channel. Both low temperature processes (≤ 550 °C) compatible with glass for flat panel displays and high temperature processes were used. NMOS TFTs show dramatic performanceimprovements up to moderate (5 to 10 nm) interlayer thicknesses. In contrast, PMOS TFTs showonly small improvements at low interlayer thicknesses (< 5 nm), after which performancedeclines. Computer simulations using an effective medium model for polycrystalline materialssuggest that in addition to interface improvement, a pseudomorphic heterojunction is formedfrom the strained Si cap and unstrained poly-Si1-xGex channel with both conduction and valenceband offsets. These offsets play a significant role in inversion layer formation.

Threshold voltage of excimer-laser-annealed polycrystalline silicon thin-film transistors

2000 ◽  
Vol 76 (17) ◽  
pp. 2442-2444 ◽  
Author(s):  
C. T. Angelis ◽  
C. A. Dimitriadis ◽  
F. V. Farmakis ◽  
J. Brini ◽  
G. Kamarinos ◽  
...  
Keyword(s):  
Thin Film ◽  
Excimer Laser ◽  
Threshold Voltage ◽  
Thin Film Transistors ◽  
Polycrystalline Silicon ◽  
Silicon Thin Film

Dynamic-Gate-Stress-Induced Degradation in Bridged-Grain Polycrystalline Silicon Thin-Film Transistors

2016 ◽  
Vol 63 (10) ◽  
pp. 3964-3970 ◽  
Author(s):  
Meng Zhang ◽  
Zhihe Xia ◽  
Wei Zhou ◽  
Rongsheng Chen ◽  
Man Wong ◽  
...  
Keyword(s):  
Thin Film ◽  
Thin Film Transistors ◽  
Polycrystalline Silicon ◽  
Silicon Thin Film

Two‐step annealed polycrystalline silicon thin‐film transistors

1996 ◽  
Vol 80 (3) ◽  
pp. 1883-1890 ◽  
Author(s):  
Kwon‐Young Choi ◽  
Min‐Koo Han
Keyword(s):  
Thin Film ◽  
Thin Film Transistors ◽  
Polycrystalline Silicon ◽  
Silicon Thin Film
Sign in / Sign up

Export Citation Format

Share Document