An Energy-Efficient Virtual Channel Power-Gating Mechanism for On-Chip Networks

Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015 ◽

10.7873/date.2015.0472 ◽

2015 ◽

Cited By ~ 14

Author(s):

Amirhossein Mirhosseini ◽

Mohammad Sadrosadati ◽

Ali Fakhrzadehgan ◽

Mehdi Modarressi ◽

Hamid Sarbazi Azad

Keyword(s):

Energy Efficient ◽

Virtual Channel ◽

Power Gating ◽

Channel Power ◽

Gating Mechanism ◽

On Chip

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Flexible Virtual Channel Power-Gating for High-Throughput and Low-Power Network-on-Chip

2014 17th Euromicro Conference on Digital System Design ◽

10.1109/dsd.2014.28 ◽

2014 ◽

Cited By ~ 2

Author(s):

Feng Wang ◽

Xiantuo Tang ◽

Qinglin Wang ◽

Zuocheng Xing ◽

Hengzhu Liu

Keyword(s):

Low Power ◽

High Throughput ◽

Network On Chip ◽

Virtual Channel ◽

Power Gating ◽

Power Network ◽

Channel Power ◽

On Chip

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Fly-Over: A Light-Weight Distributed Power-Gating Mechanism for Energy-Efficient Networks-on-Chip

2017 IEEE International Parallel and Distributed Processing Symposium (IPDPS) ◽

10.1109/ipdps.2017.77 ◽

2017 ◽

Cited By ~ 3

Author(s):

Rahul Boyapati ◽

Jiayi Huang ◽

Ningyuan Wang ◽

Kyung Hoon Kim ◽

Ki Hwan Yum ◽

...

Keyword(s):

Energy Efficient ◽

Light Weight ◽

Power Gating ◽

Distributed Power ◽

Networks On Chip ◽

Gating Mechanism ◽

On Chip

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An Energy-efficient Multi-core Restricted Boltzmann Machine Processor with On-chip Bio-plausible Learning and Reconfigurable Sparsity

2020 IEEE Asian Solid-State Circuits Conference (A-SSCC) ◽

10.1109/a-sscc48613.2020.9336135 ◽

2020 ◽

Author(s):

Jiajun Wu ◽

Xuan Huang ◽

Le Yang ◽

Liang Wang ◽

Jipeng Wang ◽

...

Keyword(s):

Energy Efficient ◽

Restricted Boltzmann Machine ◽

Boltzmann Machine ◽

On Chip

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A Crossbar Array of Analog-Digital-Hybrid Volatile Memory Synapse Cells for Energy-Efficient On-Chip Learning

2021 IEEE International Symposium on Circuits and Systems (ISCAS) ◽

10.1109/iscas51556.2021.9401530 ◽

2021 ◽

Author(s):

Janak Sharda ◽

Ritvik Sharma ◽

Debanjan Bhowmik

Keyword(s):

Energy Efficient ◽

Crossbar Array ◽

Volatile Memory ◽

On Chip

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On-chip monitoring and compensation scheme with fine-grain body biasing for robust and energy-efficient operations

2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC) ◽

10.1109/aspdac.2016.7428045 ◽

2016 ◽

Cited By ~ 2

Author(s):

A.K.M. Mahfuzul Islam ◽

Hidetoshi Onodera

Keyword(s):

Energy Efficient ◽

Compensation Scheme ◽

Fine Grain ◽

Body Biasing ◽

On Chip

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Probabilistic Analysis of Power-Gating in Network-on-Chip Routers

IEEE Transactions on Circuits & Systems II Express Briefs ◽

10.1109/tcsii.2018.2863268 ◽

2019 ◽

Vol 66 (2) ◽

pp. 242-246 ◽

Cited By ~ 1

Author(s):

Nasim Nasirian ◽

Reza Soosahabi ◽

Magdy A. Bayoumi

Keyword(s):

Probabilistic Analysis ◽

Network On Chip ◽

Power Gating ◽

On Chip

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Systematic Exploration of Energy-Efficient Application-Specific Network-on-Chip Architectures

2010 IEEE Computer Society Annual Symposium on VLSI ◽

10.1109/isvlsi.2010.60 ◽

2010 ◽

Cited By ~ 2

Author(s):

Iasonas Filippopoulos ◽

Iraklis Anagnostopoulos ◽

Alexandros Bartzas ◽

Dimitrios Soudris ◽

George Economakos

Keyword(s):

Energy Efficient ◽

Network On Chip ◽

Systematic Exploration ◽

On Chip ◽

Application Specific

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Energy-efficient optical broadcast for nanophotonic networks-on-chip

2012 Optical Interconnects Conference ◽

10.1109/oic.2012.6224445 ◽

2012 ◽

Cited By ~ 2

Author(s):

Cheng Li ◽

Mark Browning ◽

Paul V. Gratz ◽

Samuel Palermo

Keyword(s):

Energy Efficient ◽

Networks On Chip ◽

On Chip

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Active Power-Gating-Induced Power/Ground Noise Alleviation Using Parasitic Capacitance of On-Chip Memories

Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013 ◽

10.7873/date.2013.253 ◽

2013 ◽

Cited By ~ 2

Author(s):

Xuan Wang ◽

Jiang Xu ◽

Wei Zhang ◽

Xiaowen Wu ◽

Yaoyao Ye ◽

...

Keyword(s):

Parasitic Capacitance ◽

Active Power ◽

Power Gating ◽

On Chip ◽

Ground Noise

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Multi-level signaling for energy-efficient on-chip interconnects

2007 7th International Conference on ASIC ◽

10.1109/icasic.2007.4415572 ◽

2007 ◽

Author(s):

Fakhrul Zaman Rokhani ◽

Gerald E. Sobelman

Keyword(s):

Energy Efficient ◽

Multi Level ◽

On Chip

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