Active Power-Gating-Induced Power/Ground Noise Alleviation Using Parasitic Capacitance of On-Chip Memories

2013 ◽  
Author(s):  
Xuan Wang ◽  
Jiang Xu ◽  
Wei Zhang ◽  
Xiaowen Wu ◽  
Yaoyao Ye ◽  
...  
Keyword(s):  
Parasitic Capacitance ◽  
Active Power ◽  
Power Gating ◽  
On Chip ◽  
Ground Noise

Actively Alleviate Power Gating-Induced Power/Ground Noise Using Parasitic Capacitance of On-Chip Memories in MPSoC

2015 ◽  
Vol 23 (2) ◽  
pp. 266-279 ◽  
Author(s):  
Xuan Wang ◽  
Jiang Xu ◽  
Wei Zhang ◽  
Xiaowen Wu ◽  
Yaoyao Ye ◽  
...  
Keyword(s):  
Parasitic Capacitance ◽  
Power Gating ◽  
On Chip ◽  
Ground Noise

On-Chip Sensor Network for Efficient Management of Power Gating-Induced Power/Ground Noise in Multiprocessor System on Chip

2013 ◽  
Vol 24 (4) ◽  
pp. 767-777 ◽  
Author(s):  
Weichen Liu ◽  
Yu Wang ◽  
Xuan Wang ◽  
Jiang Xu ◽  
Huazhong Yang
Keyword(s):  
Sensor Network ◽  
System On Chip ◽  
Multiprocessor System ◽  
Power Gating ◽  
Efficient Management ◽  
On Chip ◽  
Ground Noise

Probabilistic Analysis of Power-Gating in Network-on-Chip Routers

2019 ◽  
Vol 66 (2) ◽  
pp. 242-246 ◽  
Author(s):  
Nasim Nasirian ◽  
Reza Soosahabi ◽  
Magdy A. Bayoumi
Keyword(s):  
Probabilistic Analysis ◽  
Network On Chip ◽  
Power Gating ◽  
On Chip

On-Chip Power Gating Technique

2012 ◽  
pp. 141-182
Author(s):  
Yusuke Kanno
Keyword(s):  
Power Gating ◽  
On Chip

Muffin: Minimally-Buffered Zero-Delay Power-Gating Technique in On-Chip Routers

2019 ◽  
Author(s):  
Hossein Farrokhbakht ◽  
Hadi Mardani Kamali ◽  
Natalie Enright Jerger
Keyword(s):  
Power Gating ◽  
On Chip

Self-Power Saving Technique in State Machine Circuit of Automatic Teller Machine Application

2019 ◽  
Vol 15 (3) ◽  
pp. 294-301
Author(s):  
Minh-Huan Vo
Keyword(s):  
Finite State Machine ◽  
Power Saving ◽  
State Machine ◽  
Active Power ◽  
The Other ◽  
State Transitions ◽  
Power Gating ◽  
Automatic Teller Machine ◽  
Current State ◽  
Finite State

In a finite state machine (FSM), there is only one active state while the other states are in idle states simultaneously. Thus, only one state is required to power up, the other states can be switched off to save active power. Normally, a backward traversing algorithm is used to label the power gating cells and extract the enable signals for combinational logic gates in reducing the active power consumption. This conventional power gating technique uses the extracted enable signals to turn ON/OFF these inserted NMOS switches. Then, a power management unit is required to manage these enable signals and detect the idle periods. The proposed self-power saving technique uses internally generated enable signals from state transitions to control NMOS switches inserted under the ground rail of each state. All internal enable signals are created to activate/deactivate the machine states at the same time. Based on the next state of the FSM, a decoder creates the enable signals for each state to do power gating in an Automatic Teller Machine (ATM) application. The isolation cell is designed to isolate the current state and next state for retaining data. Simulation results show the power saving from 31.99% at a WAIT state to 82.87% at a LOCK state, depending on the current state of the finite state machine. On average, the power loss is saved up to 63.2% in the FSM. An overhead area is about 12% compared to the conventional technique while timing overhead is under 5%.

An Energy-Efficient Virtual Channel Power-Gating Mechanism for On-Chip Networks

2015 ◽  
Author(s):  
Amirhossein Mirhosseini ◽  
Mohammad Sadrosadati ◽  
Ali Fakhrzadehgan ◽  
Mehdi Modarressi ◽  
Hamid Sarbazi Azad
Keyword(s):  
Energy Efficient ◽  
Virtual Channel ◽  
Power Gating ◽  
Channel Power ◽  
Gating Mechanism ◽  
On Chip

scholarly journals Power‐gating technique for network‐on‐chip buffers

2013 ◽  
Vol 49 (23) ◽  
pp. 1438-1440 ◽  
Author(s):  
M.R. Casu ◽  
M.K. Yadav ◽  
M. Zamboni
Keyword(s):  
Network On Chip ◽  
Power Gating ◽  
On Chip

On-chip resonant supply noise reduction utilizing switched parasitic capacitors of sleep blocks with tri-mode power gating structure

2011 ◽  
Author(s):  
Jinmyoung Kim ◽  
Toru Nakura ◽  
Hidehiro Takata ◽  
Koichiro Ishibashi ◽  
Makoto Ikeda ◽  
...  
Keyword(s):  
Noise Reduction ◽  
Power Gating ◽  
Supply Noise ◽  
On Chip

Run-Time Power-Gating Techniques for Low-Power On-Chip Networks

2010 ◽  
pp. 21-43
Author(s):  
Hiroki Matsutani ◽  
Michihiro Koibuchi ◽  
Hiroshi Nakamura ◽  
Hideharu Amano
Keyword(s):  
Low Power ◽  
Power Gating ◽  
Run Time ◽  
On Chip
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