Sub-10 nm FinFETs and Tunnel-FETs: From Devices to Systems

Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015 ◽

10.7873/date.2015.0870 ◽

2015 ◽

Author(s):

Ankit Sharma ◽

A. Arun Goud ◽

Kaushik Roy

Keyword(s):

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Influence of Gate and Channel Engineering on Multigate Tunnel FETs: A Review

Computational Advancement in Communication Circuits and Systems - Lecture Notes in Electrical Engineering ◽

10.1007/978-981-13-8687-9_31 ◽

2019 ◽

pp. 345-355 ◽

Author(s):

Ritam Dutta ◽

Sukumar Chandra Konar ◽

Nitai Paitya

Keyword(s):

Channel Engineering ◽

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A methodical survey on present state of art for electrostatically-doped tunnel FETs and its future prospects

Materials Today Proceedings ◽

10.1016/j.matpr.2021.01.963 ◽

2021 ◽

Author(s):

Preeti Sharma ◽

Jaya Madan ◽

Rahul Pandey ◽

Rajnish Sharma

Keyword(s):

Present State ◽

Future Prospects ◽

Tunnel Fets ◽

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Perspectives on Dielectric Modulated Biosensing in Silicon Tunnel FETs

Silicon ◽

10.1007/s12633-021-00945-4 ◽

2021 ◽

Author(s):

Manan Mehta ◽

Rupam Goswami

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Investigation of Variability in Device Design on Saturation Characteristics of Nanowire Tunnel FETs

Silicon ◽

10.1007/s12633-021-01183-4 ◽

2021 ◽

Author(s):

Abhishek Acharya

Keyword(s):

Device Design ◽

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Controlling the ambipolar current in ultrathin SOI tunnel FETs using the back-bias effect

Journal of Computational Electronics ◽

10.1007/s10825-020-01484-8 ◽

2020 ◽

Vol 19 (2) ◽

pp. 658-667 ◽

Author(s):

Tripuresh Joshi ◽

Balraj Singh ◽

Yashvir Singh

Keyword(s):

Bias Effect ◽

Ambipolar Current ◽

Tunnel Fets ◽

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Influence of Localized Interface Charges on Drain Current of Dual-Material Double-Gate Tunnel FETs

2018 3rd International Conference for Convergence in Technology (I2CT) ◽

10.1109/i2ct.2018.8529418 ◽

2018 ◽

Author(s):

Sanjay Kumar ◽

Kamlaksha Baral ◽

Sweta Chander ◽

P. K. Singh ◽

Kunal Singh ◽

...

Keyword(s):

Drain Current ◽

Double Gate ◽

Interface Charges ◽

Tunnel Fets ◽

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VLS-grown silicon nanowires — Dopant deactivation and tunnel FETs

2010 Silicon Nanoelectronics Workshop ◽

10.1109/snw.2010.5562587 ◽

2010 ◽

Author(s):

M. T. Bjork ◽

K. E. Moselund ◽

H. Schmid ◽

H. Ghoneim ◽

S. Karg ◽

...

Keyword(s):

Silicon Nanowires ◽

Tunnel Fets ◽

Dopant Deactivation

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(Invited) Vertical Tunnel FETs Using III-V Nanowire/Si Heterojunctions

ECS Transactions ◽

10.1149/06103.0081ecst ◽

2014 ◽

Vol 61 (3) ◽

pp. 81-89 ◽

Author(s):

K. Tomioka ◽

T. Fukui

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Simulation study of nanowire tunnel FETs

70th Device Research Conference ◽

10.1109/drc.2012.6257023 ◽

2012 ◽

Author(s):

Andreas Schenk ◽

Reto Rhyner ◽

Mathieu Luisier ◽

Cedric Bessire

Keyword(s):

Simulation Study ◽

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Investigation of doping in InAs/GaSb hetero-junctions for tunnel-FETs

2016 IEEE Silicon Nanoelectronics Workshop (SNW) ◽

10.1109/snw.2016.7578028 ◽

2016 ◽

Author(s):

Davide Cutaia ◽

Heinz Schmid ◽

Mattias Borg ◽

Kirsten Moselund ◽

Nicolas Bologna ◽

...

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