Controlling the ambipolar current in ultrathin SOI tunnel FETs using the back-bias effect

Tripuresh Joshi; Balraj Singh; Yashvir Singh

doi:10.1007/s10825-020-01484-8

Controlling the ambipolar current in ultrathin SOI tunnel FETs using the back-bias effect

Journal of Computational Electronics ◽

10.1007/s10825-020-01484-8 ◽

2020 ◽

Vol 19 (2) ◽

pp. 658-667 ◽

Cited By ~ 3

Author(s):

Tripuresh Joshi ◽

Balraj Singh ◽

Yashvir Singh

Keyword(s):

Bias Effect ◽

Ambipolar Current ◽

Tunnel Fets ◽

Ultrathin Soi

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Charge Pumping in Ultrathin SOI Tunnel FETs: Impact of Back-Gate Voltage

ECS Transactions ◽

10.1149/08903.0111ecst ◽

2019 ◽

Vol 89 (3) ◽

pp. 111-120

Author(s):

Carlos Diaz Llorente ◽

Christoforos G. Theodorou ◽

Jean-Pierre Colinge ◽

Sorin Cristoloveanu ◽

Sebastien Martinie ◽

...

Keyword(s):

Gate Voltage ◽

Back Gate ◽

Charge Pumping ◽

Tunnel Fets ◽

Ultrathin Soi

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An analytical back-gate bias effect model for ultrathin SOI CMOS devices

IEEE Transactions on Electron Devices ◽

10.1109/16.202788 ◽

1993 ◽

Vol 40 (4) ◽

pp. 755-765 ◽

Cited By ~ 23

Author(s):

J. Sim ◽

J.B. Kuo

Keyword(s):

Gate Bias ◽

Bias Effect ◽

Back Gate ◽

Effect Model ◽

Ultrathin Soi ◽

Soi Cmos

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Controlling the Drain Side Tunneling Width to Reduce Ambipolar Current in Tunnel FETs Using Heterodielectric BOX

IEEE Transactions on Electron Devices ◽

10.1109/ted.2015.2478955 ◽

2015 ◽

Vol 62 (11) ◽

pp. 3882-3886 ◽

Cited By ~ 80

Author(s):

Shubham Sahay ◽

Mamidala Jagadesh Kumar

Keyword(s):

Drain Side ◽

Ambipolar Current ◽

Tunnel Fets ◽

Tunneling Width

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Hetero-gate Dielectric with Hetero Dielectric BOX for Suppressing Ambipolar Current in Tunnel FETs

2020 International Conference on Intelligent Engineering and Management (ICIEM) ◽

10.1109/iciem48762.2020.9160161 ◽

2020 ◽

Author(s):

Irfan Ahmad Pindoo ◽

Sanjeet K. Sinha

Keyword(s):

Gate Dielectric ◽

Ambipolar Current ◽

Tunnel Fets

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Suppression of ambipolar current in tunnel FETs using drain-pocket: Proposal and analysis

Superlattices and Microstructures ◽

10.1016/j.spmi.2017.11.002 ◽

2018 ◽

Vol 113 ◽

pp. 261-270 ◽

Cited By ~ 26

Author(s):

Shelly Garg ◽

Sneh Saurabh

Keyword(s):

Ambipolar Current ◽

Tunnel Fets

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Simulation of Ge/(Si)GeSn hetero-junction tunnel FETs with suppressed ambipolar current

2018 18th International Workshop on Junction Technology (IWJT) ◽

10.1109/iwjt.2018.8330307 ◽

2018 ◽

Cited By ~ 1

Author(s):

Yongwang Zhang ◽

Suyuan Wang ◽

Jun Zheng ◽

Chunlai Xue ◽

Chuanbo Li ◽

...

Keyword(s):

Ambipolar Current ◽

Tunnel Fets

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An analysis on the ambipolar current in Si double-gate tunnel FETs

Solid-State Electronics ◽

10.1016/j.sse.2011.11.009 ◽

2012 ◽

Vol 70 ◽

pp. 67-72 ◽

Cited By ~ 115

Author(s):

Hraziia ◽

Andrei Vladimirescu ◽

Amara Amara ◽

Costin Anghel

Keyword(s):

Double Gate ◽

Ambipolar Current ◽

Tunnel Fets

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Charge Pumping in Ultrathin SOI Tunnel FETs: Impact of Back-Gate Voltage

ECS Meeting Abstracts ◽

10.1149/ma2019-01/23/1198 ◽

2019 ◽

Keyword(s):

Gate Voltage ◽

Back Gate ◽

Charge Pumping ◽

Tunnel Fets ◽

Ultrathin Soi

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Back-gate bias effect on the subthreshold behavior and the switching performance in an ultrathin SOI CMOS inverter operating at 77 and 300 K

IEEE Transactions on Electron Devices ◽

10.1109/16.168724 ◽

1992 ◽

Vol 39 (12) ◽

pp. 2781-2790 ◽

Cited By ~ 10

Author(s):

J.B. Kuo ◽

W.C. Lee ◽

J.-H. Sim

Keyword(s):

Gate Bias ◽

Cmos Inverter ◽

Bias Effect ◽

Back Gate ◽

Switching Performance ◽

Ultrathin Soi ◽

Soi Cmos

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Bias Effect on Validity and Reliability of a Rating Scale

Measurement and Evaluation in Guidance ◽

10.1080/00256307.1970.12022440 ◽

1970 ◽

Vol 3 (2) ◽

pp. 70-75

Author(s):

James A. Bitter

Keyword(s):

Rating Scale ◽

Validity And Reliability ◽

Bias Effect

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