Design and Assertion Based Verification of RISC-V Processor Subsystems

2021 ◽  
Vol 7 (3) ◽  
Author(s):  
Shruthi . ◽  
Jamuna S
Keyword(s):  
High Speed ◽  
Branch Prediction ◽  
Floating Point ◽  
Processor Architecture ◽  
Pipeline Architecture ◽  
Description Language ◽  
Instruction Fetch ◽  
Hardware Description ◽  
Floating Point Unit ◽  
Back Stage

RISC-V is an open, free standard architecture. As its open-source architecture, it can be used in multiple applications like embedded processors, IoT, artificial intelligence, machine learning, military and defense applications. The parameters like throughput, performance, high speed etc., become essential in designing processor architecture. Pipelining is one such unique feature supported by RISC-V ISA, which basically involves the execution of multiple instructions in single cycle. This feature helps in improving the performance of the processor architecture. RISC-V ISA supports five stages of pipelining they are instruction fetch, instruction decode, execute, memory and write-back stage. The work covered in this paper involves the design and implementation of the subsystems of the RISC-V ISA which are present in different stages of pipeline architecture. The subsystems included in this work are Floating Point Unit (FPU) of Execute stage, Branch Prediction Unit (BPU) of instruction fetch stage, Forwarding Unit of execution stage, Operand Logic of decode stage and Floating-Point register file of Write-back stage. These subsystems are designed using Verilog Hardware Description Language in Xilinx ISE. Followed by the implementation the verification of the floating-point unit and the forwarding unit is performed using System Verilog Assertions in QuestaSim. The Assertion coverage report for the same is extracted.

scholarly journals SYNTHESIS AND FPGA–IMPLEMENTATION BASED NEURAL TECHNIQUE OF A NONLINEAR ADC MODEL

2014 ◽  
pp. 27-33
Author(s):  
Mounir Bouhedda ◽  
Mokhtar Attari
Keyword(s):  
Integrated Circuit ◽  
Field Programmable Gate Array ◽  
High Speed ◽  
Hardware Description Language ◽  
Description Language ◽  
Analog To Digital ◽  
Field Programmable ◽  
Hardware Description ◽  
Nonlinear Analog ◽  
Very High

The aim of this paper is to introduce a new architecture using Artificial Neural Networks (ANN) in designing a 6-bit nonlinear Analog to Digital Converter (ADC). A study was conducted to synthesise an optimal ANN in view to FPGA (Field Programmable Gate Array) implementation using Very High-speed Integrated Circuit Hardware Description Language (VHDL). Simulation and tests results are carried out to show the efficiency of the designed ANN.

A modeling method of algorithm-hardware based on SysML

2021 ◽  
Author(s):  
Liu Yue ◽  
Zhao Chun ◽  
Zhang Lin
Keyword(s):  
Graphical Models ◽  
Integrated Circuit ◽  
High Speed ◽  
System Modeling ◽  
Modeling Method ◽  
Description Language ◽  
Hardware Description ◽  
Circuit And System ◽  
Graphical System ◽  
Hardware Circuit

In the process of complex product design, modeling in different fields and different disciplines is often involved. Designers often face many different development kits, platforms, and theories, among which significant differences exist. Especially in the process of algorithm-hardware implementation, it is necessary to have mastery of the knowledge including algorithm, hardware, circuit, and system engineering. In this paper, a modeling method of algorithm-hardware based on SysML is proposed to reduce the difficulty of algorithm-hardware modeling. By using the method, the designers who do not know the knowledge of hardware can also easily build the algorithm-hardware model. In this method, a method of graphical system modeling based on SysML is used, where the elements of the algorithm-hardware model are described by SysML graphical models. Then, the SysML graphical models are converted to Very-High-Speed Integrated Circuit Hardware Description Language. At last, a detecting algorithm of random number is complemented by the modeling method in this paper and the simulation results are presented at the conclusion.

Implementation of High Speed Self Switching Frequency Agile RADAR

2013 ◽  
Vol 3 (1) ◽  
pp. 11
Author(s):  
K Jansi Lakshmi ◽  
K Surya Narayana Reddy
Keyword(s):  
High Speed ◽  
Switching Frequency ◽  
Frequency Diversity ◽  
Description Language ◽  
General Application ◽  
Frequency Agile ◽  
On Line ◽  
Hardware Description ◽  
Effective Function ◽  
Self Adaptive

<div class="WordSection1"><p><strong><a href="mailto:[email protected]"></a></strong></p></div><strong> </strong>The radar has to resist diversified jamming; High Speed self-adaptive frequency   agility   is   an   important   and   effective function  for radars to resist jamming.  The procedure to achieve this function are described, and the function is realized with FPGA using Hardware description  Language, the validity is proved by on- line sampling and simulation. The High speed self-adaptive frequency agility module can analyze the type of jamming to select  transmitting  frequency  to avoid the frequencies which have interference, under frequency       diversity  and  fixed  frequency, respectively. The   general   application   on   a   searching   radar shows that the module has good real-time and anti- jamming capacity.

scholarly journals High Throughput Implementation of the Keccak Hash Function Using the Nios-II Processor

Technologies ◽  
2020 ◽  
Vol 8 (1) ◽  
pp. 15
Author(s):  
Argyrios Sideris ◽  
Theodora Sanida ◽  
Minas Dasygenis
Keyword(s):  
Integrated Circuit ◽  
Hash Function ◽  
High Speed ◽  
Critical Role ◽  
Optimization Techniques ◽  
Floating Point ◽  
Throughput Optimization ◽  
Nios Ii ◽  
Hash Algorithm ◽  
Hardware Description

Presently, cryptographic hash functions play a critical role in many applications, such as digital signature systems, security communications, protocols, and network security infrastructures. The new standard cryptographic hash function is Secure Hash Algorithm 3 (SHA-3), which is not vulnerable to attacks. The Keccak algorithm is the winner of the NIST competition for the adoption of the new standard SHA-3 hash algorithm. In this work, we present hardware throughput optimization techniques for the SHA-3 algorithm using the Very High Speed Integrated Circuit Hardware Description Language (VHDL) programming language for all output lengths in the Keccak hash function (224, 256, 384 and 512). Our experiments were performed with the Nios II processor on the FPGA Arria 10 GX (10AX115N2P45E1SG). We applied two architectures, one without custom instruction and one with floating point hardware 2. Finally, we compare the results with other existing similar designs and found that the proposed design with floating point 2 optimizes throughput (Gbps) compared to existing FPGA implementations.

scholarly journals Design and Analysis of Radix-8/4/2 64b/32b Integer Divider Using COMPASS Cell Library

VLSI Design ◽  
2000 ◽  
Vol 11 (4) ◽  
pp. 331-338 ◽  
Author(s):  
Chua-Chin Wang ◽  
Chenn-Jung Huang ◽  
I-Yen Chang
Keyword(s):  
High Speed ◽  
Hardware Description Language ◽  
Verilog Hdl ◽  
Description Language ◽  
Throughput Rate ◽  
Cell Library ◽  
Conversion Algorithm ◽  
Hardware Description ◽  
Simulation Results

A high speed 64b/32b integer divider employing digit-recurrence division method and the on-the-fly conversion algorithm, wherein a fast normalizer is included, which is used as the pre-processor of the proposed integer divider. For the sake of enhancing throughput rate, the proposed divider uses a mixed radix-8/4/2 division instead of the traditional radix-2 division. On-the-fly remainder adjustment is also realized in the converter module of the divider. The entire design is written in Verilog HDL (hardware description language) employing COMPASS 0.6 μm 1P3M cell library (V3.0), and then synthesized by SYNOPSYS. The simulation results indicate that our design is a better option than the existing long divider designs.

scholarly journals Designing High-Performance Fuzzy Controllers Combining IP Cores and Soft Processors

2012 ◽  
Vol 2012 ◽  
pp. 1-11 ◽  
Author(s):  
Oscar Montiel-Ross ◽  
Jorge Quiñones ◽  
Roberto Sepúlveda
Keyword(s):  
Parallel Programming ◽  
High Speed ◽  
High Performance ◽  
Hardware Description Language ◽  
System Response ◽  
Description Language ◽  
Tuning Method ◽  
Hardware Description ◽  
Ip Cores ◽  
Fuzzy Pd

This paper presents a methodology to integrate a fuzzy coprocessor described in VHDL (VHSIC Hardware Description Language) to a soft processor embedded into an FPGA, which increases the throughput of the whole system, since the controller uses parallelism at the circuitry level for high-speed-demanding applications, the rest of the application can be written in C/C++. We used the ARM 32-bit soft processor, which allows sequential and parallel programming. The FLC coprocessor incorporates a tuning method that allows to manipulate the system response. We show experimental results using a fuzzy PD+I controller as the embedded coprocessor.

scholarly journals Space Vector Pulse Width Modulation for High-Speed Induction Motor Implemented in Nios II Softcore Processor

2018 ◽  
Vol 3 (1) ◽  
pp. 99-107
Author(s):  
Maciej Chojowski
Keyword(s):  
Induction Motor ◽  
Pulse Width ◽  
High Speed ◽  
Pulse Width Modulation ◽  
Classical Method ◽  
Hardware Description Language ◽  
Description Language ◽  
Space Vector ◽  
Nios Ii ◽  
Hardware Description

Abstract The purpose of the article was to present the idea of space vector pulse width modulation (SVPWM) and implementation in Nios II softcore processor. The SVPWM module was described in a classical method in hardware description language both as an independent structure and as an additional component to softcore processor. The available methods were compared, and the experiment was carried out in the laboratory to test implemented SVPWM algorithm using high-speed induction motor.

scholarly journals FPGA configuration of an alloyed correlated branch predictor used with RISC processor for educational purposes

2021 ◽  
Vol 11 (1) ◽  
pp. 265
Author(s):  
Hadeel SH. Mahmood
Keyword(s):  
Prediction Accuracy ◽  
High Speed ◽  
Description Language ◽  
Risc Processor ◽  
Branch Predictor ◽  
Hardware Description ◽  
Prediction Techniques ◽  
Sort Algorithm ◽  
Processor Speed ◽  
Very High

Instructions pipelining is one of the most outstanding techniques used in improving processor speed; nonetheless, these pipelined stages are constantly facing stalls that caused by nested conditional branches. During the execution of nested conditional branches, the behavior of the running branch depends on the history information of the previous ones; therefore, these branches have the greatest effect in reducing the prediction accuracy of a branch predictor among conditional branches. The purpose of this research is to reduce the stall cycles caused by correlated branches misprediction by introducing a hardware model of a branch predictor that combines both local and global prediction techniques. This predictor integrates the prediction characteristics of the alloyed predictor with those of the correlated predictor. the predictor design which implemented in VHDL (Very high-speed IC hardware description language) was inserted in previously designed MIPS (microprocessor without interlocked pipelined stages) processor and its prediction accuracy was confirmed by executing a program using the selection sort algorithm to sort 100 input numbers of different combinations ascendingly.

scholarly journals PERANCANGAN DAN IMPLEMENTASI ARSITEKTUR DEMAPPER 64-QAM DI FPGA

2017 ◽  
Author(s):  
Achmad Rizal Mauludin ◽  
Rina Pudji Astuti ◽  
Denny Darlis
Keyword(s):  
High Speed ◽  
Short Message Service ◽  
Hardware Description Language ◽  
Short Message ◽  
Least Significant Bit ◽  
Description Language ◽  
Error Process ◽  
Message Service ◽  
Hardware Description ◽  
Gate Array

Sistem telekomunikasi bertujuan untuk mengirimkan sinyal dari sumber informasi yang dapatberbentuk suara, pesan singkat atau Short Message Service (SMS), gambar, video dan layanan data ke tujuanyang diinginkan. Informasi yang akan dikirimkan akan diubah menjadi sinyal yang dapat dilewati mediatransmisi, dan agar sinyal yang diterima disisi penerima dapat dibaca, diperlukan demodulator yang dapatmengubah sinyal yang diterima menjadi informasi seperti yang dikirimkan. Demodulator 64-QuadratureAmplitude Modulation (QAM) adalah salah satu jenis demodulator yang mampu mendemodulasi sinyalfrekuensi tinggi.Dalam tugas akhir ini, telah dirancang dan diimplementasikan demapper 64-QAM yang merupakansub blok demodulator, pada FPGA (Field Programable Gate Array) yang menggunakan bahasa pengkodeanVery High Speed Integrated Cicuit (VHSIC) Hardware Description Language (VHDL) Fungsi dari blok iniadalah untuk memetakan balik simbol-simbol masukan dengan amplitudo dan fasa yang berbeda-beda yangsebelumnya telah direpresentasikan ke dalam bentuk bit-bit pada sisi pengirim. Pemetaan balik ini mengubahsimbol-simbol tersebut menjadi bit-bit informasi yang masih berupa bit-bit inphase dan quadrature.Dari hasil penelitian ini, untuk kondisi ideal atau gangguan didapatkan output di sisi penerima berupasebuah bit-bit informasi yang sama dengan bit-bit informasi yang dikirimkan pada sisi pengirim. Sedangkanuntuk kondisi ada gangguan, hasil outputnya masih sama dengan bit-bit informasi selama bit yang digangguadalah enam bit dari LSB (Least Significant bit), untuk tujuh bit yang diganggu error process yang terjadiadalah 21,8310 % sedangkan untuk empat belas bit yang diganggu error process yang terjadi sebesar 96,9072%.

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