Generalized Receiver with Parallel Interference Cancellation for Multiuser Detection

Parallel interference cancellation is considered as a simple yet effective multiuser detector for direct -sequence code-division multiple-access (DS-CDMA) systems. However, system performance be deteriorated due to unreliable interference cancellation in the early stages. Thus, a detector with the partial parallel interfere-nce cancellation in which the partial cancellation factors are introduced to control the interference cancellation level has been developed as a remedy. Although the partial cancellation factors are crucial, complete solutions for their optimal values are not available. In this paper, we consider a two-stage decoupled generalized receiver with the partial parallel interference cancellation. Using the minimum bit error rate (BER) criterion, we derive a complete set of optimal partial cancellation factors. This includes the optimal partial cancellation factors for pe-riodic and aperiodic spreading codes in channels with the additive white Gaussian noise and multipath chann-els. Simulation results demonstrate that the considered theoretical optimal partial cancellation factors agree clo-sely with empirical ones. The proposed two-stage generalized receiver with the partial parallel interference can-cellation using the derived optimal partial cancellation factors outperforms not only a two-stage, but also a three-stage conventional generalized receiver with the full parallel interference cancellation.

Analysis of Multiuser Detectors and Performance improvement in DS-CDMA system using Multistage Multiuser Detection Techniques

Among the various interferences, the Multiple Access Interference (MAI) is a significant issue in Direct Sequence Code Division Multiple Access (DS-CDMA) system due to its users. When the number of users is increasing the MAI is likewise increments, subsequently the system performance progressively diminishes particularly in fading environment. In this paper, the system performance is improved by the proposed multistage multiuser detection technique called Multistage Multiuser Differencing Partial Parallel Interference Cancellation (DPPIC). This is the combination of Partial Parallel Interference Cancellation (PPIC) and Differencing Parallel Interference Cancellation (DPIC). Multistage Multiuser Parallel Interference Cancellation (PIC) and Multistage Multiuser PPIC techniques that exist gave improved system performance meaning as the number of stages increases the MAI decreases but at the cost of increased computational complexity. The computational complexity was reduced by utilizing Multistage Difference PIC (DPIC) technique but with no improvement in the performance. To improve the system performance as well as reduce the computational complexity Multistage Multiuser Partial Differencing Parallel Interference Cancellation (PDPIC) method can be used. The simulation results show that the proposed DPPIC technique performs better than PIC, PPIC and PDPIC in terms of Bit Error Rate (BER) versus normalized signal amplitude ( i.e., E b / N 0 ), but computational complexity slightly more than PDPIC in fading environment.

GPU Accelerated PIC and SIC for OFDM-NOMA

Non-orthogonal multiple access (NOMA) is a candidate multiple access scheme for the fifth-generation (5G) cellular networks. In NOMA systems, all users operate at the same frequency and time, which poses a challenge in the decoding process at the receiver side. In this work, the two most popular receiver structures, successive interference cancellation (SIC) and parallel interference cancellation (PIC) receivers, for NOMA reverse channel are implemented on a graphics processing unit (GPU) and compared. Orthogonal frequency division multiplexing (OFDM) is considered. The high computational complexity of interference cancellation receivers undermines the potential deployment of NOMA systems. GPU acceleration, however, challenges this weakness, and our numerical results show speedups of about from 75–220-times as compared to a multi-thread implementation on a central processing unit (CPU). SIC and PIC multi-thread execution time on different platforms reveals the potential of GPU in wireless communications. Furthermore, the successful decoding rates of the SIC and PIC are evaluated and compared in terms of bit error rate.