ПЕРСПЕКТИВЫ РАЗВИТИЯ ТЕХНОЛОГИИ 3D-МИКРОСБОРОК ДЛЯ АППАРАТУРЫ КОСМИЧЕСКОГО ПРИМЕНЕНИЯ

ассмотрены параметры и конструктивные особенности систем в корпусе, разработанных на основе технологии 3D-монтажа, - схем памяти для аппаратуры космического применения. Предложены структура и схемотехника микросборки бортового компьютера на основе конструктива и технологии гибридного монтажа 3D-структур и отдельных кристаллов, включая CPLD (Complex Programmable Logic Device). Рассмотрен альтернативный принцип конструирования ячейки памяти, специализированной для применения в CPLD-микросхемах. Показаны результаты проектирования CPLD средней емкости для приборов космического применения. В качестве ключевой технологической базы использовался техпроцесс SOI 180 нм HV, 3D-структуры созданы с использованием TSV (Through-silicon via) интерпозеров (Interposer).

Technique to Dynamically Reconfigure FPGAs using Control Registers

Due to increased use of FPGAs computation intensive applications, the need for embedded processing system integrated with programmable logic device has also increased. Configuration of programmable logic device by the processing system through its interface improves the efficiency of the device. In order to operate as a stand-alone device and to have a better efficiency, the programmable logic device must be capable of dynamically programming its own configuration memory. In this paper, we propose a configurable logic block with a control register to improve performance of the programmable logic device. The control register acts like a decentralized configuration memory array which can be programmed by other such configurable logic blocks. The FPGAs are fault tolerant devices with repetitive structures requiring high packaging density. This property of FPGA enables the use of CNTFETs for design of FPGAs. CNTFETs offer high trans-conductance and 1-D ballistic transport of electrons and holes which minimizes the power consumed by the FPGA. The proposed control register based architecture was implemented using Cadence Virtuoso using virtual source CNTFET model from Stanford University. A power reduction of 17.62% is achieved using CNTFETs when compared with FINFET at same technology node and the architecture was verified for various configurations of the control register