Inverter design with positive feedback field-effect transistors

As the physical size of semiconductor devices continues to be aggressively scaled down, feedback field-effect transistors (FBFET) with a positive feedback mechanism among a few promising steep switching devices have received attention as next-generation switching devices. Conventional FBFETs have been studied to explore their device performance. However, this has been restricted to the case of single FBFET; basic circuit designs with FBFETs have not been investigated extensively. In this work, we propose an inverter circuit design with silicon-on-insulator (SOI) FBFETs; we verified this inverter design with mixed-mode technology computer-aided design simulation. The basic principles and mechanisms for designing FBFET inverter circuits are explained because their configuration is different from conventional inverters. In addition, the device parameters necessary to optimize circuit construction are introduced for logic device applications.

Enhancement of InSe Field-Effect-Transistor Performance against Degradation of InSe Film in Air Environment

The degradation of InSe film and its impact on field effect transistors are investigated. After the exposure to atmospheric environment, 2D InSe flakes produce irreversible degradation that cannot be stopped by the passivation layer of h-BN, causing a rapid decrease for InSe FETs performance, which is attributed to the large number of traps formed by the oxidation of 2D InSe and adsorption to impurities. The residual photoresist in lithography can cause unwanted doping to the material and reduce the performance of the device. To avoid contamination, a high-performance InSe FET is achieved by a using hard shadow mask instead of the lithography process. The high-quality channel surface is manifested by the hysteresis of the transfer characteristic curve. The hysteresis of InSe FET is less than 0.1 V at Vd of 0.2, 0.5, and 1 V. And a high on/off ratio of 1.25 × 108 is achieved, as well relative high Ion of 1.98 × 10−4 A and low SS of 70.4 mV/dec at Vd = 1 V are obtained, demonstrating the potential for InSe high-performance logic device.

In-Memory Hamming Error-Correcting Code in Memristor Crossbar

This paper proposes a in-memory Hamming error-correcting code (ECC) in memristor crossbar array (CBA). Based on unique I-V characteristic of complementary resistive switching (CRS) memristor, this work discovers that a combination of three memristors behaves as a stateful exclusive-OR (XOR) logic device. In addition, a two-step (build-up and fire) current-mode CBA driving scheme is proposed to realize a linear increment of the build-up voltage that is proportional to the number of low-resistance state (LRS) memristors in the array. Combining the proposed XOR logic device and the driving scheme, we realize a complete stateful XOR logic, which enables a fully functional in-memory Hamming ECC, including parity bit generation and storage followed by syndrome vector calculation/readout. The proposed technique is verified by simulation program with integrated circuit emphasis (SPICE) simulations, with a Verilog-A CRS memristor model and a commercial 45-nm CMOS process design kit (PDK). The verification results prove that the proposed in-memory ECC perfectly detects error regardless of data patterns and error locations with enough margin.

In-Memory Hamming Error-Correcting Code in Memristor Crossbar

This paper proposes a in-memory Hamming error-correcting code (ECC) in memristor crossbar array (CBA). Based on unique I-V characteristic of complementary resistive switching (CRS) memristor, this work discovers that a combination of three memristors behaves as a stateful exclusive-OR (XOR) logic device. In addition, a two-step (build-up and fire) current-mode CBA driving scheme is proposed to realize a linear increment of the build-up voltage that is proportional to the number of low-resistance state (LRS) memristors in the array. Combining the proposed XOR logic device and the driving scheme, we realize a complete stateful XOR logic, which enables a fully functional in-memory Hamming ECC, including parity bit generation and storage followed by syndrome vector calculation/readout. The proposed technique is verified by simulation program with integrated circuit emphasis (SPICE) simulations, with a Verilog-A CRS memristor model and a commercial 45-nm CMOS process design kit (PDK). The verification results prove that the proposed in-memory ECC perfectly detects error regardless of data patterns and error locations with enough margin.

Development of a fuzzy expert system for power transformer diagnostics

In this paper, an expert information system for assessing the technical condition of a power transformer is developed. The system will work on the basis of the fuzzy logic device, and provide operational information about the state of the power transformer. The paper uses fuzzy inference algorithms. The R programming language is used to write a program that uses fuzzy logic. We analyzed the data of chromatographic analysis of gases dissolved in oil, as well as the data of thermal imaging images, identifying the most heated points in power transformers. A database of fuzzy logic rules has been formed. Several examples of defuzzification of the results obtained by the center of gravity method are given. As a result of the program, a three-dimensional graph was obtained that characterizes the surface of the fuzzy output. The developed software package allows you to detect defects in working electrical equipment at an early stage of their development, which not only prevents a sudden shutdown of production as a result of an accident, but also significantly reduces the cost of repairing equipment and increases its service life

ПЕРСПЕКТИВЫ РАЗВИТИЯ ТЕХНОЛОГИИ 3D-МИКРОСБОРОК ДЛЯ АППАРАТУРЫ КОСМИЧЕСКОГО ПРИМЕНЕНИЯ

ассмотрены параметры и конструктивные особенности систем в корпусе, разработанных на основе технологии 3D-монтажа, - схем памяти для аппаратуры космического применения. Предложены структура и схемотехника микросборки бортового компьютера на основе конструктива и технологии гибридного монтажа 3D-структур и отдельных кристаллов, включая CPLD (Complex Programmable Logic Device). Рассмотрен альтернативный принцип конструирования ячейки памяти, специализированной для применения в CPLD-микросхемах. Показаны результаты проектирования CPLD средней емкости для приборов космического применения. В качестве ключевой технологической базы использовался техпроцесс SOI 180 нм HV, 3D-структуры созданы с использованием TSV (Through-silicon via) интерпозеров (Interposer).

A Decoder – Look up Tables for FPGAs

The FPGA (Field-Programmable Gate Array) has recently become the popular hardware and so-called LUTs (Look up Tables) are the basic of the FPGAs logic. For example, n-LUT is the MOS pass transistors multiplexer 2n-1 which input data receive SRAM cells logic function configuration (user’s projects Truth Table). Address inputs of the LUT are the variables. Therefore, we get one n-arguments logic function for the actual FPGA configuration. To get m functions (even with the same n-arguments) we should take m LUT. Authors propose a novel Decoder n-LUT (n-DC LUT), which makes possible to get m functions with the same n-arguments, like in Program Logic Array (PLA) CPLD (Complex Programmable Logic Device). DC LUT activates one of the 2n product terms outputs. Combined with OR product terms we can get m functions with the same n-arguments. To do this option we can use, for example, FPGAs typical connections units. The restriction of Meade-Conway for the FPGAs allows n=3 in one tree. Two 3-LUTs with one 1-LUTs form 4-LUT. Modern Adaptive Logic Modules (ALM) have n=8, but not all possible functions are implemented. The article deals with the design and investigation of some variants 3-DC LUT: with pull up output resistors, with orthogonal output circuits, with orthogonal transistors for each pass transistor. Simulation confirms the feasibility of the proposed method and shows that DC LUT with orthogonal output circuits is better variant of the systems realization in terms of current consumption and time delay at large n. A further development of the ALM concept may be the introduction of adaptive DC LUT, which, by tuning, can calculate single LUT function or 2n decoder functions. The proposed elements allow to increase the functionality of the FPGAs.