scholarly journals High performance modified bit-vector based packet classification module on low-cost FPGA

2021 ◽  
Vol 11 (5) ◽  
pp. 3855
Author(s):  
Anita P. ◽  
Manju Devi
Keyword(s):  
High Performance ◽  
Low Cost ◽  
Packet Classification ◽  
Total Power ◽  
Network Systems ◽  
Pipelined Architecture ◽  
Bit Vector ◽  
And Performance ◽  
Comparative Results ◽  
Application Requirements

The packet classification plays a significant role in many network systems, which requires the incoming packets to be categorized into different flows and must take specific actions as per functional and application requirements. The network system speed is continuously increasing, so the demand for the packet classifier also increased. Also, the packet classifier's complexity is increased further due to multiple fields should match against a large number of rules. In this manuscript, an efficient and high performance modified bitvector (MBV) based packet classification (PC) is designed and implemented on low-cost Artix-7 FPGA. The proposed MBV based PC employs pipelined architecture, which offers low latency and high throughput for PC. The MBV based PC utilizes <2% slices, operating at 493.102 MHz, and consumes 0.1 W total power on Artix-7 FPGA. The proposed PC considers only 4 clock cycles to classify the incoming packets and provides 74.95 Gbps throughput. The comparative results in terms of hardware utilization and performance efficiency of proposed work with existing similar PC approaches are analyzed with better constraints improvement.

scholarly journals Design of a Low Latency and High Throughput Packet Classification Module on FPGA Platform

2020 ◽  
Vol 9 (4) ◽  
pp. 1468-1474
Keyword(s):  
High Speed ◽  
Network Performance ◽  
Packet Classification ◽  
Total Power ◽  
Network Systems ◽  
Chip Area ◽  
Packet Header ◽  
Rule Set ◽  
Bit Vector ◽  
Ip Packet

The Packet classification method plays a significant role in most of the Network systems. These systems categories the incoming packets in various flows and takes suitable action based on the requirements. If the size of the network is vast and complexity will arise to perform the different operations, which affects the network performance and other constraints also. So there is the demand for high-speed packet classifiers to reduce the network complexity and improve the network performance. In this article, The Bit vector Packet classifier (BV-PC) Module is designed to improve the network system performance and overcome the existing limitation of Packet classification approaches on FPGA. The BV-PC Module contains Packet generation Unit (PGU) to receive the valid incoming packets, Memory Unit (MU) to store valid packets, Header Extractor Unit (HEU) extracts the IP Header address information from the Valid packets, The BV-Based Source and Destination Address (BV-SA, BV-DA) unit receives the IP packet header Information and Process with BV based rule set and aggregates the BV-SA and BV-DA outputs, Priority Encoder encodes the Highest priority BV Rule for the generation of Classified output. The BV-PC utilizes <2% Chip area (slices), works at 509.38MHz, and consumed Less 0.103 W of total Power on Artix-7 FPGA. The BV-PC operates with a latency of 5 clock cycles and works at 815.03Mpps throughput. The BV-PC is compared with existing approaches and provides Better improvements in Hardware constraints.

RF-MEMS Components and Networks for High-Performance Reconfigurable Telecommunication and Wireless Systems

2012 ◽  
Vol 81 ◽  
pp. 65-74 ◽  
Author(s):  
Jacopo Iannacci ◽  
Giuseppe Resta ◽  
Paola Farinelli ◽  
Roberto Sorrentino
Keyword(s):  
High Performance ◽  
Microelectromechanical Systems ◽  
Rf Mems ◽  
Low Cost ◽  
Impedance Matching ◽  
Phase Shifters ◽  
Rf Systems ◽  
Mems Technology ◽  
And Performance ◽  
Rf Performance

MEMS (MicroElectroMechanical-Systems) technology applied to the field of Radio Frequency systems (i.e. RF-MEMS) has emerged in the last 10-15 years as a valuable and viable solution to manufacture low-cost and very high-performance passive components, like variable capacitors, inductors and micro-relays, as well as complex networks, like tunable filters, reconfigurable impedance matching networks and phase shifters, and so on. The availability of such components and their integration within RF systems (e.g. radio transceivers, radars, satellites, etc.) enables boosting the characteristics and performance of telecommunication systems, addressing for instance a significant increase of their reconfigurability. The benefits resulting from the employment of RF-MEMS technology are paramount, being some of them the reduction of hardware redundancy and power consumption, along with the operability of the same RF system according to multiple standards. After framing more in detail the whole context of RF MEMS technology, this paper will provide a brief introduction on a typical RF-MEMS technology platform. Subsequently, some relevant examples of lumped RF MEMS passive elements and complex reconfigurable networks will be reported along with their measured RF performance and characteristics.

Advanced SiP Packaging Technologies of IPD for Mobile Applications

2010 ◽  
Vol 2010 (DPC) ◽  
pp. 1-20
Author(s):  
Geun Sik Kim ◽  
Kai Liu ◽  
Flynn Carson ◽  
Seung Wook Yoon ◽  
Meenakshi Padmanathan
Keyword(s):  
High Performance ◽  
Low Cost ◽  
Autonomous Systems ◽  
System Level ◽  
Design And Technology ◽  
Wafer Level ◽  
Future Technology ◽  
Rf Transceivers ◽  
And Performance ◽  
3D Stacking

IPD technology was originally developed as a way to replace bulky discrete passive components, but it¡¯s now gaining popularity in ESD/EMI protection applications, as well as in RF, high-brightness LED silicon sub-mounts, and digital and mixed-signal devices. Already well known as a key enabler of system-in-packages (SiPs), IPDs enable the assembly of increasingly complete and autonomous systems with the integration of diverse electronic functions such as sensors, RF transceivers, MEMS, power amplifiers, power management units, and digital processors. The application area for IPD will continue to evolve, especially as new packaging technology, such as flipchip, 3D stacking, wafer level packaging become available to provide vertical interconnections within the IPD. New applications like silicon interposers will become increasingly significant to the market. Currently the IPD market is being driven primarily by RF or wireless packages and applications including, but not limited to, cell phones, WiFi, GPS, WiMAX, and WiBro. In particular, applications and products in the emerging RF CMOS market that require a low cost, smaller size, and high performance are driving demand. In order to get right products in size and performance, packaging design and technology should be considered in device integration and implemented together in IPD designs. In addition, a comprehensive understanding of electrical and mechanical properties in component and system level design is important. This paper will highlight some of the recent advancements in SiP technology for IPD and integration as well as what is developed to address future technology requirements in IPD SiP solutions. The advantage and applications of SiP solution for IPD will be presented with several examples of IPD products. The design, assembly and packaging challenges and performance characteristics will be also discussed.

scholarly journals Review on Pressure Sensors: A Perspective from Mechanical to Micro-electro-mechanical systems

2021 ◽  
Author(s):  
Ankur Gupta
Keyword(s):  
High Performance ◽  
Low Cost ◽  
Pressure Sensors ◽  
Micro Electro Mechanical System ◽  
Single Chip ◽  
Micro Electro Mechanical Systems ◽  
Compact Size ◽  
Wide Range ◽  
Fabrication Procedure ◽  
Application Requirements

Swiftly emerging research prospects in the Micro-Electro-Mechanical System (MEMS) enable to build of complex and sophisticated microstructures on a substrate containing moving masses, cantilevers, flexures, levers, linkages, dampers, gears, detectors, actuators, and many more on a single chip. One of the MEMS initial products that emerged into the micro-system technology is the MEMS pressure sensor. Because of their high performance, low cost, and compact size, these sensors are extensively being adopted in numerous applications viz., aerospace, automobile, and bio-medical domain, etc. These application requirements drive and impose tremendous conditions on sensor design to overcome the tedious design and fabrication procedure before its reality. MEMS-based pressure sensors enable a wide range of pressure measurements as per the application requirements. Considering its vast utility in industries, this paper presents a detailed review of MEMS-based pressure sensors and their wide area of applications, their design aspects, and challenges, to provide state of an art gist to the researchers of a similar domain in one place.

scholarly journals Enabling Packet Classification with Low Update Latency for SDN Switch on FPGA

2020 ◽  
Vol 12 (8) ◽  
pp. 3068 ◽  
Author(s):  
Chenglong Li ◽  
Tao Li ◽  
Junnan Li ◽  
Zilin Shi ◽  
Baosheng Wang
Keyword(s):  
Real Time ◽  
Field Programmable Gate Array ◽  
High Performance ◽  
Recursive Algorithm ◽  
Packet Classification ◽  
Experimental Results ◽  
The Core ◽  
Core Function ◽  
Field Programmable ◽  
Bit Vector

Field Programmable Gate Array (FPGA) is widely used in real-time network processing such as Software-Defined Networking (SDN) switch due to high performance and programmability. Bit-Vector (BV)-based approaches can implement high-performance multi-field packet classification, on FPGA, which is the core function of the SDN switch. However, the SDN switch requires not only high performance but also low update latency to avoid controller failure. Unfortunately, the update latency of BV-based approaches is inversely proportional to the number of rules, which means can hardly support the SDN switch effectively. It is reasonable to split the ruleset into sub-rulesets that can be performed in parallel, thereby reducing update latency. We thus present SplitBV for the efficient update by using several distinguishable exact-bits to split the ruleset. SplitBV consists of a constrained recursive algorithm for selecting the bit positions that can minimize the latency and a hybrid lookup pipeline. It can achieve a significant reduction in update latency with negligible memory growth and comparable high performance. We implement SplitBV and evaluate its performance by simulation and FPGA prototype. Experimental results show that our approach can reduce 73% and 36% update latency on average for synthetic 5-tuple rules and OpenFlow rules respectively.

scholarly journals Properties of Foamed Lightweight High-Performance Phosphogypsum-Based Ternary System Binder

2020 ◽  
Vol 10 (18) ◽  
pp. 6222 ◽  
Author(s):  
Girts Bumanis ◽  
Jelizaveta Zorica ◽  
Diana Bajare
Keyword(s):  
Ternary System ◽  
High Performance ◽  
Raw Materials ◽  
Low Cost ◽  
Construction Materials ◽  
Mineralogical Composition ◽  
Point Of View ◽  
Raw Material ◽  
Total Energy Consumption ◽  
And Performance

The potential of phosphogypsum (PG) as secondary raw material in construction industry is high if compared to other raw materials from the point of view of availability, total energy consumption, and CO2 emissions created during material processing. This work investigates a green hydraulic ternary system binder based on waste phosphogypsum (PG) for the development of sustainable high-performance construction materials. Moreover, a simple, reproducible, and low-cost manufacture is followed by reaching PG utilization up to 50 wt.% of the binder. Commercial gypsum plaster was used for comparison. High-performance binder was obtained and on a basis of it foamed lightweight material was developed. Low water-binder ratio mixture compositions were prepared. Binder paste, mortar, and foamed binder were used for sample preparation. Chemical, mineralogical composition and performance of the binder were evaluated. Results indicate that the used waste may be successfully employed to produce high-performance binder pastes and even mortars with a compression strength up to 90 MPa. With the use of foaming agent, lightweight (370–700 kg/m3) foam concrete was produced with a thermal conductivity from 0.086 to 0.153 W/mK. Water tightness (softening coefficient) of such foamed material was 0.5–0.64. Proposed approach represents a viable solution to reduce the environmental footprint associated with waste disposal.

Fabrication and Performance Analysis of PMMA Substrate Diffuser/Nozzle Micro-Pump by CNC Milling Machine

2009 ◽  
Vol 60-61 ◽  
pp. 198-201
Author(s):  
Li Tian ◽  
Wei Wang ◽  
Xiao Wei Liu ◽  
Ying Zhang ◽  
Shu Yi Ji
Keyword(s):  
High Performance ◽  
Low Cost ◽  
Maximum Flow ◽  
Microfluidic System ◽  
Milling Process ◽  
Cnc Milling ◽  
Micro Pump ◽  
Orifice Flow ◽  
And Performance ◽  
Nozzle Structure

A new low cost high performance PMMA micropump, developed for microfluidic system, is presented. According to the orifice flow theory, a diffuser/nozzle structure is fabricated with precision milling process, and packaged with the film-sealing at the condition of thermal bonding process. The size parameter of the diffuser/nozzle structure is 2.5mm *150µm, 8° conical angle, the volume of PMMA micropump is 14×14×2.5 mm3. And experimental results show that the PMMA micropump can produce a maximum back pressure of 1906.1Pa and a maximum flow rate of 564µL/min under 220 V, 500Hz squired wave power supply.

Recent Advances in Pyroelectric Ceramics and Thin Films for Applications in Uncooled Infra-Red Sensor Arrays

2006 ◽  
Vol 45 ◽  
pp. 2503-2513 ◽  
Author(s):  
Roger W. Whatmore
Keyword(s):  
Thin Films ◽  
High Performance ◽  
Spatial Information ◽  
Low Cost ◽  
Sensor Arrays ◽  
Production Costs ◽  
Healthcare Applications ◽  
Infra Red ◽  
And Performance ◽  
Materials Used

Pyroelectric infra-red detector arrays provide an attractive solution to the problem of collecting spatial information on the IR distribution in a scene. They have the property that they are only sensitive to changes in the IR flux. This means that they are particularly-well suited to the monitoring of movements of people in applications such as retail outlets and in safety and healthcare applications. The applications of low cost arrays with limited (few hundred elements) for people sensing and imaging radiometry will be illustrated. The performances and costs of uncooled pyroelectric arrays are ultimately driven by the materials used. For this reason, continuous improvements in materials technology are important. In the area of bulk ceramics, it is possible to obtain significant improvements in both production costs and performance though the use of tape-cast, functionally-gradient materials. The use of directly-deposited ferroelectric thin films on silicon ASIC’s is offering considerable potential for low cost high performance pyroelectric arrays. The challenges involved in developing such materials will be discussed.

scholarly journals A 79 dBΩ 1.2 GHz Low-Noise Single-Ended CMOS Transimpedance Amplifier for High-Performance OTDR Applications

2019 ◽  
Vol 15 (2) ◽  
pp. 113-118
Author(s):  
Agata Romanova ◽  
Vaidotas Barzdenas
Keyword(s):  
High Performance ◽  
Low Cost ◽  
Low Noise ◽  
Cmos Process ◽  
Transimpedance Amplifier ◽  
Output Buffer ◽  
Noise Current ◽  
Resistive Feedback ◽  
Optical Time ◽  
And Performance

AbstractThe work reports on the design and performance of a low-noise low-cost CMOS transimpedance amplifier (TIA). The proposed circuit shall be employed in optical time-domain reflectometers and is implemented using an affordable 0.18 µm 1.8 V CMOS process. The approach preserves the benefits of a classical feedback structure while addressing the noise problem of conventional feed-forward and resistive feedback architectures via the usage of noise-efficient capacitive feedback. Circuit-level modifications are proposed to mitigate the voltage headroom and DC current issues. The suggested design achieves a total gain of 82 dBΩ (79 dBΩ after the output buffer) within the bandwidth of 1.2 GHz while operating with a total input capacitance of 0.7 pF. The simulated average input-referred noise current density is below 1.8 pA/sqrt(Hz) with the power consumption of the complete amplifier including the output buffer being 21 mW.

scholarly journals Enhancing the performance of the aggregated bit vector algorithm in network packet classification using GPU

2019 ◽  
Vol 5 ◽  
pp. e185 ◽  
Author(s):  
Mahdi Abbasi ◽  
Razieh Tahouri ◽  
Milad Rafiee
Keyword(s):  
Graphics Processing Units ◽  
High Speed ◽  
Parallel Implementation ◽  
Packet Classification ◽  
Experimental Results ◽  
Analysis Method ◽  
Network Systems ◽  
Computationally Intensive ◽  
Bit Vector ◽  
Graphics Processing

Packet classification is a computationally intensive, highly parallelizable task in many advanced network systems like high-speed routers and firewalls that enable different functionalities through discriminating incoming traffic. Recently, graphics processing units (GPUs) have been exploited as efficient accelerators for parallel implementation of software classifiers. The aggregated bit vector is a highly parallelizable packet classification algorithm. In this work, first we present a parallel kernel for running this algorithm on GPUs. Next, we adapt an asymptotic analysis method which predicts any empirical result of the proposed kernel. Experimental results not only confirm the efficiency of the proposed parallel kernel but also reveal the accuracy of the analysis method in predicting important trends in experimental results.

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