Minimizing Ancilla Inputs and Garbage Outputs of Reversible BCD Multiplier

Over the last decades, designing reversible arithmetic circuits is one of the interesting research areas because of its ability to reduce power consumption in the circuits. This paper proposes two new design approaches of reversible binary-coded decimal (BCD) multiplier. The realization of such BCD multiplier has been achieved through binary multipliers, multiplexers, and a binary-to-BCD converter. Four types of multiplications, viz. [Formula: see text], [Formula: see text], [Formula: see text], and [Formula: see text] multiplications, have been utilized for such binary multiplication and are implemented parallelly as a combined multiplier to reduce ancilla inputs (AIs) and garbage outputs (GOs). We also propose a novel reversible BCD adder for a reversible binary-to-BCD converter with reducing AIs and GOs. The first design of the reversible BCD multiplier is integrated with the proposed BCD adder in the binary-to-BCD converter. Furthermore, the proposed reversible BCD adder is modified to reduce the AIs and the GOs, which is then integrated into the second design of the reversible BCD multiplier. The results offer appreciable reductions of AIs and GOs by at least [Formula: see text]16% and [Formula: see text]43%, respectively, compared to the existing designs found in the literature.

First Steps in Creating Online Testable Reversible Sequential Circuits

Synthesis of reversible sequential circuits is a very new research area. It has been shown that such circuits can be implemented using quantum dot cellular automata. Other work has used traditional designs for sequential circuits and replaced the flip-flops and the gates with their reversible counterparts. Our earlier work uses a direct feedback method without any flip-flops, improving upon the replacement technique in both quantum cost and ancilla inputs. We present here a further improved version of the direct feedback method. Design examples show that the proposed method produces better results than our earlier method in terms of both quantum cost and ancilla inputs. We also propose the first technique for online testing of single line faults in sequential reversible circuits.

Design and Analysis of Multiple Parameters Optimized n-Bit Reversible Magnitude Comparators

Reversible logic has gained its importance in the field of low power digital design. In any digital system, the comparator plays an important role in determining whether the two referenced numbers are either equal, greater or lesser. This work deals with optimization of existing reversible comparator designs and also proposes a new multiplexer-based logic for the design of reversible comparator along with design methodology for [Formula: see text]-bit comparators. The proposed design is optimized for multiple performance parameters compared to the existing state-of-the-art designs. The proposed multiplexer-based design has 51.9% improvement in quantum cost, 50% in garbage outputs and 62% in ancilla inputs. These optimized designs find application predominantly in the field of quantum computing for low power signal processing, parallel computing, memories, digital system design and multi-processing.

Design Methodologies for Reversible Logic Based Barrel Shifters

Barrel shifter is an integral component of processor datapaths in computing systems since it can shift and rotate multiple bits in a single cycle. Furthermore, reversible logic has applications in emerging computing paradigms such as quantum computing, quantum dot cellular automata, optical computing, etc. In this work, we propose efficient methodologies for designing reversible barrel shifters. The proposed methodologies are designed using Fredkin gate and Feynman gate (FG). The Fredkin gate is used because it can implement a 2:1 MUX with minimum quantum cost, minimum number of ancilla inputs and garbage outputs, and the Feynman gate is used to avoid a fanout since a fanout is not allowed in reversible logic. In the existing literature, design methodologies are limited to the design of a ([Formula: see text]) reversible left rotator that can only perform the left rotate operation. This work explores the other primary functionalities of a reversible barrel shifter such as the design of a reversible: (i) logical right shifter, (ii) universal right shifter that supports logical right shifter, arithmetic right shifter and right rotate operation, (iii) bidirectional logical shifter and (iv) universal bidirectional shifter that supports bidirectional logical and arithmetic shifter and rotate operations. The other types of reversible barrel shifters can also be easily designed by making minor modifications in the proposed methodologies. The proposed design methodologies are generic in nature and can be implemented using any barrel shifter of ([Formula: see text]) size, where n and k are the number of data bits and shift value, respectively. In order to minimize the number of ancilla inputs and garbage outputs, strategies such as the implementation of an n number of 2:1 MUXes as a chain of n Fredkin gates and the mapping of the two different 2:1 MUXes that are controlled by a common control signal but having the swapped controlled signals on a single Fredkin gate, are utilized. The design methodologies are evaluated in terms of the number of garbage outputs, the number of ancilla inputs and quantum cost. For a ([Formula: see text]) reversible barrel shifter, the relations between the varying values of n and k and their impact on the number of garbage outputs, the number of ancilla inputs and quantum cost are also established to help the designers in choosing an efficient barrel shifter according to their design needs.