EXPLOITING INSTRUCTION REUSE TO IMPROVE THE PERFORMANCE OF DUAL INSTRUCTION EXECUTION

Dual instruction execution (DIE) is an effective instruction-level temporal redundancy technique to improve the datapath reliability against transient errors for superscalar microprocessors. However, previous study shows that the performance overhead of dual instruction execution on an out-of-order core is substantial, primarily due to the serious resource contention problems such as the ALU bandwidth. In this paper, we propose a novel approach to reducing the performance overhead of DIE without compromising the datapath reliability. In the proposed scheme, both the primary and the duplicate instructions of DIE can exploit the ECC-protected instruction reuse buffer (IRB) for mitigating the resource contention of DIE by minimizing the number of dynamic instructions executed, leading to better performance without impacting the reliability of DIE. Our experiments indicate that the proposed approach can reduce the performance loss of dual instruction execution by up to 70.8%, with 51.1% on average, and can reduce the performance loss of DIE–IRB by up to 17.2%, with 7.1% on average, while providing reliability comparable to DIE or DIE–IRB.

REDUCING THE ENERGY DISSIPATION OF THE ISSUE QUEUE BY EXPLOITING NARROW IMMEDIATE OPERANDS

In contemporary superscalar microprocessors, issue queue is a considerable energy dissipating component due its complex scheduling logic. In addition to the energy dissipated for scheduling activities, read and write lines of the issue queue entries are also high energy consuming pieces of the issue queue. When these lines are used for reading and writing unnecessary information bits, such as the immediate operand part of an instruction that does not use the immediate field or the insignificant higher order bits of an immediate operand that are in fact not needed, significant amount of energy is wasted. In this paper, we propose two techniques to reduce the energy dissipation of the issue queue by exploiting the immediate operand files of the stored instructions: firstly by storing immediate operands in separate immediate operand files rather than storing them inside the issue queue entries and secondly by issue queue partitioning based on widths of immediate operands of instructions. We present our performance results and energy savings using a cycle accurate simulator and testing the design with SPEC2K benchmarks and 90 nm CMOS (UMC) technology.

MODIFYING THE DATA-HOLDING COMPONENTS OF THE MICROPROCESSORS FOR ENERGY EFFICIENCY

Storage components are a major source of energy dissipation in modern superscalar microprocessors. As the instruction windows get larger with each generation of processors, register files and other structures that hold intermediate data become larger and dissipate more power. Therefore it is important to find new ways to reduce the energy dissipation of data holding components. Many values written to and read from these storage components are known to require fewer bits than is provided by the storage space. Upper order bits of these values are unnecessary and energy savings can be achieved by not writing and reading these bits. Floating value data has different characteristics and offer special energy savings opportunities. In this paper we analyze the bit-level statistics of data values and propose simple modifications to data holding components that save significant energy inside the processors. Our results show that by using simple modifications on the storage components it is possible to achieve 40% reduction in the integer register file energy dissipation and up to 60% reduction in the immediate field of the issue queue. We also show that energy dissipation can be reduced by half for some floating point benchmarks by identifying values that indicate a zero operand.