EXPLOITING INSTRUCTION REUSE TO IMPROVE THE PERFORMANCE OF DUAL INSTRUCTION EXECUTION

Dual instruction execution (DIE) is an effective instruction-level temporal redundancy technique to improve the datapath reliability against transient errors for superscalar microprocessors. However, previous study shows that the performance overhead of dual instruction execution on an out-of-order core is substantial, primarily due to the serious resource contention problems such as the ALU bandwidth. In this paper, we propose a novel approach to reducing the performance overhead of DIE without compromising the datapath reliability. In the proposed scheme, both the primary and the duplicate instructions of DIE can exploit the ECC-protected instruction reuse buffer (IRB) for mitigating the resource contention of DIE by minimizing the number of dynamic instructions executed, leading to better performance without impacting the reliability of DIE. Our experiments indicate that the proposed approach can reduce the performance loss of dual instruction execution by up to 70.8%, with 51.1% on average, and can reduce the performance loss of DIE–IRB by up to 17.2%, with 7.1% on average, while providing reliability comparable to DIE or DIE–IRB.