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Silicon-Proven Timing Signoff Methodology Using Hazard-Free Robust Path Delay Tests

2020 ◽  
Vol 37 (4) ◽  
pp. 7-13
Author(s):  
Ankit Shah ◽  
Raman Nayyar ◽  
Arani Sinha
Keyword(s):  
Path Delay ◽  
Delay Tests

Optimizing delay tests at the memory boundary

2015 ◽  
Author(s):  
Kelly A. Ockunzzi ◽  
Michael R. Ouellette ◽  
Kevin W. Gorman
Keyword(s):  
Delay Tests

Silicon Evaluation of Cell-Aware ATPG Tests and Small Delay Tests

2014 ◽  
Author(s):  
Fan Yang ◽  
Sreejit Chakravarty ◽  
Arun Gunda ◽  
Nicole Wu ◽  
Jianyu Ning
Keyword(s):  
Small Delay ◽  
Delay Tests

Silicon evaluation of faster than at-speed transition delay tests

2012 ◽  
Author(s):  
S Chakravarty ◽  
N. Devta-Prasanna ◽  
A. Gunda ◽  
J. Ma ◽  
F. Yang ◽  
...  
Keyword(s):  
Transition Delay ◽  
Delay Tests

Low Test Data Volume Low Power At-Speed Delay Tests Using Clock-Gating

2011 ◽  
Author(s):  
Elham K. Moghaddam ◽  
Janusz Rajski ◽  
Sudhakar M. Reddy ◽  
Jakub Janicki
Keyword(s):  
Low Power ◽  
Test Data ◽  
Clock Gating ◽  
Data Volume ◽  
Delay Tests
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