A Comparative Study of Low Power Testing Techniques for Digital Circuits

2017 ◽  
Vol 7 (7) ◽  
pp. 412 ◽  
Author(s):  
Suhas B Shirol ◽  
Rajashekar B Shettar
Keyword(s):  
Comparative Study ◽  
Low Power ◽  
Vlsi Design ◽  
Systems Design ◽  
Linear Feedback ◽  
Computing Systems ◽  
Low Power Testing ◽  
Digital Vlsi ◽  
Portable Computing ◽  
Power Testing

In recent years, with fast growth of mobile communication and portable computing systems, design for low power has become the challenge in the field of Digital VLSI design. The main focus of the paper is to make a comparative study of low power Linear Feedback Shift Register (LFSR) architecture such as Built In Self Test (BIST), it has been often seen that during test mode process the power consumed is  much higher, when compared to that of normal mode process test as there is high switching activity in the nodes of Circuit Under Test(CUT) during testing.

scholarly journals A Glitch-Free Novel DET-FF in 22 nm CMOS for Low-Power Application

2018 ◽  
Vol 2018 ◽  
pp. 1-6 ◽  
Author(s):  
Sumitra Singar ◽  
N. K. Joshi ◽  
P. K. Ghosh
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Performance ◽  
Vlsi Design ◽  
Total System ◽  
Clock Frequency ◽  
Flip Flop ◽  
Digital Vlsi ◽  
Feedback Structure ◽  
Power Application

Dual edge triggered (DET) techniques are most liked choice for the researchers in the field of digital VLSI design because of its high-performance and low-power consumption standard. Dual edge triggered techniques give the similar throughput at half of the clock frequency as compared to the single edge triggered (SET) techniques. Dual edge triggered techniques can reduce the 50% power consumption and increase the total system power savings. The low-power glitch-free novel dual edge triggered flip-flop (DET-FF) design is proposed in this paper. Still now, existing DET-FF designs are constructed by using either C-element circuit or 1P-2N structure or 2P-1N structure, but the proposed novel design is designed by using the combination of C-element circuit and 2P-1N structure. In this design, if any glitch affects one of the structures, then it is nullified by the other structure. To control the input loading, the two circuits are merged to share the transistors connected to the input. In the proposed design, we have used an internal dual feedback structure. The proposed design reduces the delay and power consumption and increases the speed and efficiency of the system.

ISC: Reconfigurable Scan-Cell Architecture for Low Power Testing

2005 ◽  
Author(s):  
H. Esmaeilzadeh ◽  
S. Shamshiri ◽  
P. Saeedi ◽  
Z. Navabi
Keyword(s):  
Low Power ◽  
Low Power Testing ◽  
Cell Architecture ◽  
Power Testing
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