A reversible circuit synthesis algorithm with progressive increase of controls in generalized Toffoli gates

We present a new algorithm for synthesis of reversible circuits for arbitrary n-bit bijective functions. This algorithm uses generalized Toffoli gates, which include positive and negative controls. Our algorithm is divided into two parts. First, we use partially controlled gen- eralized Toffoli gates, progressively increasing the number of controls. Second, exploring the properties of the representation of permutations in disjoint cycles, we apply generalized Toffoli gates with controls on all lines except for the target line. Therefore, new in the method is the fact that the obtained circuits use first low cost gates and consider increasing costs towards the end of the synthesis. In addition, we employ two bidirectional synthesis strategies to improve the gate count, which is the metric used to compare the results obtained by our algorithm with the results presented in the literature. Accordingly, our experimental results consider all 3-bit bijective functions and twenty widely used benchmark functions. The results obtained by our synthesis algorithm are competitive when compared with the best results known in the literature, considering as a complexity metric just the number of gates, as done by alternative best heuristics found in the literature. For example, for all 3-bit bijective functions using generalized Toffoli gates library, we obtained the best so far average count of 5.23.

On the dependence of the complexity and depth of reversible circuits consisting of NOT, CNOT, and 2-CNOT gates on the number of additional inputs

The paper is concerned with the complexity and depth of reversible circuits consisting of NOT, CNOT, and 2-CNOT gates under constraints on the number of additional inputs. We study the Shannon functions for the complexity L(n, q) and depth D(n, q) of a reversible circuit implementing a map f : ℤ 2 n → ℤ 2 n $f\colon \mathbb{Z}_2^n \to \mathbb{Z}_2^n$ under the condition that the number of additional inputs q is in the range 8 n < q ≲ n 2 n − ⌈ n / ϕ ( n ) ⌉ $8n < q \mathbin{\lower.3ex\hbox{$\buildrel<\over {\smash{\scriptstyle\sim}\vphantom{_x}}$}} n{2^{n - \left\lceil {n{\rm{ }}/\phi (n)} \right\rceil }}$ , where ϕ(n) → ∞ and n / ϕ(n) − log2 n → ∞ as n → ∞. We establish the upper estimates L ( n , q ) ≲ 2 n + 8 n 2 n / ( log 2 ( q − 4 n ) − log 2 n − 2 ) $L(n,q) \lesssim 2^n + 8n2^n \mathop / (\log_2 (q-4n) - \log_2 n - 2)$ and D ( n , q ) ≲ 2 n + 1 ( 2 , 5 + log 2 n − log 2 ( log 2 ( q − 4 n ) − log 2 n − 2 ) ) $D(n,q) \lesssim 2^{n+1}(2,5 + \log_2 n - \log_2 (\log_2 (q - 4n) - \log_2 n - 2))$ for this range of q. The asymptotics L ( n , q ) ≍ n 2 n / log 2 q $L(n,q) \asymp n2^n \mathop / \log_2 q$ is established for q such that n 2 ≲ q ≲ n 2 n − ⌈ n / ϕ ( n ) ⌉ ${n^2} \mathbin{\lower.3ex\hbox{$\buildrel<\over {\smash{\scriptstyle\sim}\vphantom{_x}}$}} q \mathbin{\lower.3ex\hbox{$\buildrel<\over {\smash{\scriptstyle\sim}\vphantom{_x}}$}} n{2^{n - \left\lceil {n{\rm{ }}/\phi (n)} \right\rceil }}$ , where ϕ(n) → ∞ and n / ϕ(n) − log2 n → ∞ as n → ∞.

An Efficient Design for Testability Approach of Reversible Logic Circuits

Reversible circuits have been extensively investigated because of their applications in areas of quantum computing or low-power design. A reversible circuit is composed of only reversible gates and allow computations from primary inputs to primary outputs and vice-versa. In the last decades, synthesis of reversible circuits received significant interest. Additionally, testing of these kinds of circuits has been studied which included different fault models and test approaches dedicated for reversible circuits only. The analysis of testability issues in a reversible circuit commonly involves the detection of the missing gate faults that may occur during the physical realizations of the reversible gates. In this paper, we propose a design for testability (DFT) technique for reversible circuits in which the gates of a circuit are clustered into different sets and the gates from each cluster are then connected to an additional input line where, the additional line acts as an extra control input to the corresponding gate. Such arrangement makes it possible to achieve [Formula: see text] fault detection in any reversible circuit with a small increase in quantum cost. Experimental evaluations confirm that the proposed DFT technique incurs less quantum cost overhead with [Formula: see text] fault detection compared to existing DFT techniques for reversible circuits.