An Efficient Design for Testability Approach of Reversible Logic Circuits

2020 ◽  
pp. 2150094
Author(s):  
Joyati Mondal ◽  
Arighna Deb ◽  
Debesh K. Das
Keyword(s):  
Fault Detection ◽  
Low Power Design ◽  
Design For Testability ◽  
Control Input ◽  
Quantum Cost ◽  
Efficient Design ◽  
Additional Line ◽  
Reversible Circuits ◽  
Reversible Circuit ◽  
Additional Input

Reversible circuits have been extensively investigated because of their applications in areas of quantum computing or low-power design. A reversible circuit is composed of only reversible gates and allow computations from primary inputs to primary outputs and vice-versa. In the last decades, synthesis of reversible circuits received significant interest. Additionally, testing of these kinds of circuits has been studied which included different fault models and test approaches dedicated for reversible circuits only. The analysis of testability issues in a reversible circuit commonly involves the detection of the missing gate faults that may occur during the physical realizations of the reversible gates. In this paper, we propose a design for testability (DFT) technique for reversible circuits in which the gates of a circuit are clustered into different sets and the gates from each cluster are then connected to an additional input line where, the additional line acts as an extra control input to the corresponding gate. Such arrangement makes it possible to achieve [Formula: see text] fault detection in any reversible circuit with a small increase in quantum cost. Experimental evaluations confirm that the proposed DFT technique incurs less quantum cost overhead with [Formula: see text] fault detection compared to existing DFT techniques for reversible circuits.

Reversible Circuits Synthesis from Functional Decision Diagrams by using Node Dependency Matrices

2019 ◽  
Vol 29 (05) ◽  
pp. 2050079
Author(s):  
Suzana Stojković ◽  
Radomir Stanković ◽  
Claudio Moraga ◽  
Milena Stanković
Keyword(s):  
Data Structure ◽  
Optimal Order ◽  
Decision Diagrams ◽  
Circuit Synthesis ◽  
Quantum Cost ◽  
Dependency Matrix ◽  
Bottom Level ◽  
Reversible Circuits ◽  
Reversible Circuit ◽  
Toffoli Gates

Decision diagrams are a data structure suitable for reversible circuit synthesis. Functional decision diagrams (FDDs) are particularly convenient in synthesis with Toffoli gates, since the functional expressions for decomposition rules used in them are similar to the functional expressions of Toffoli gates. The main drawback of reversible circuit synthesis based on decision diagrams is the usually large number of ancilla lines. This paper presents two methods for the reduction of the number of ancilla lines in reversible circuits derived from FDDs by selecting the order of implementation of nodes. In the first method, nodes are implemented by levels, starting from the bottom level to the top. The method uses appropriately defined level dependency matrices for choosing the optimal order of implementation of nodes at the same level. In this way, the optimization is performed level by level. The second method uses a diagram dependency matrix expressing mutual dependencies among all the nodes in the diagram. This method is computationally more demanding than the first method, but the reductions of both the number of lines and the Quantum cost of the circuits are larger.

Novel Synthesis Methodology for Fault Tolerant Reversible Circuits by Bounded Model Checking for Linear Temporal Logic

2015 ◽  
Vol 24 (06) ◽  
pp. 1550091 ◽  
Author(s):  
Ming-Cui Li ◽  
Ri-Gui Zhou
Keyword(s):  
Model Checking ◽  
Temporal Logic ◽  
Fault Tolerant ◽  
Linear Temporal Logic ◽  
Bounded Model Checking ◽  
Quantum Cost ◽  
Step Method ◽  
Synthesis Time ◽  
Reversible Circuits ◽  
Reversible Circuit

Reversible circuit is of interest due to the characteristics of low energy consumption. This paper proposes a new scheme for synthesizing fault tolerant reversible circuits. A two-step method is put forward to convert an irreversible function into a parity-preserving reversible circuit. By introducing model checking for linear temporal logic, we construct a finite state machine to synthesize small reversible gates from elementary 1-qubit and 2-qubit gates, which is more automatic than the methods proposed previously. Constrains are increased so as to reduce the synthesis time in the two step method. The parity-preserving gate constructed by the two-step method has characteristics of low quantum cost because the quantum representation obtained from the counterexample for a given function in each step has the minimum quantum cost. In order to further reduce the quantum cost and decrease the synthesis time, the semi parity-preserving gates are put forward for the first time. These gates are parity-preserving when the auxiliary input is set to 0 and opposite parity when 1. Maintaining good robustness of the system in performing specific function, semi parity-preserving gate is conducive to detecting the stuck-at fault and partial gate fault in reversible circuits. The innovation of this paper is introducing the formal method to synthesis small fault tolerant gate, so as to construct the circuit with robust (semi) parity-preserving gates.

scholarly journals Synthesis of reversible circuits for large reversible functions

2010 ◽  
Vol 23 (3) ◽  
pp. 273-286 ◽  
Author(s):  
Nouraddin Alhagi ◽  
Maher Hawash ◽  
Marek Perkowski
Keyword(s):  
Data Structure ◽  
Real Time ◽  
Large Scale ◽  
Optimal Solution ◽  
Truth Table ◽  
Synthesis Process ◽  
Quantum Cost ◽  
Reversible Circuits ◽  
Gate Count ◽  
Reversible Circuit

This paper presents a new algorithm MP (multiple pass) to synthesize large reversible binary circuits without ancilla bits. The well-known MMD algorithm for synthesis of reversible circuits requires to store a truth table (or a Reed-Muller - RM transform) as a 2n vector to represent a reversible function of n variables. This representation prohibits synthesis of large functions. However, in MP we do not store such an exponentially growing data structure. The values of minterms are calculated in MP dynamically, one-by-one, from a set of logic equations that specify the reversible circuit to be designed. This allows for synthesis of large scale reversible circuits (30-bits), which is not possible with any existing algorithm. In addition, our unique multi-pass approach where the circuit is synthesized with various, yet specific, minterm orders yields quasi-optimal solution. The algorithm returns a description of the quasi-optimal circuit with respect to gate count or to its 'quantum cost'. Although the synthesis process in MP is relatively slower, the solution is found in real-time for smaller circuits of 8 bits or less.

Initial Value Compensation with Additional Input Considering Optimization of Control Input

2008 ◽  
Vol 128 (10) ◽  
pp. 1219-1227 ◽  
Author(s):  
Noriaki Hirose ◽  
Yasuhisa Terachi ◽  
Motohiro Kawafuku ◽  
Makoto Iwasaki ◽  
Hiromu Hirai
Keyword(s):  
Control Input ◽  
Initial Value ◽  
Additional Input

Periodic controller for guaranteed simultaneous stabilization of two plants with robust zero error tracking

2018 ◽  
Vol 233 (5) ◽  
pp. 480-490
Author(s):  
Arindam Chakraborty ◽  
Jayati Dey
Keyword(s):  
Design Methodology ◽  
Linear Time ◽  
Pole Placement ◽  
Control Input ◽  
Efficient Design ◽  
Simultaneous Stabilization ◽  
Bounded Control ◽  
Linear Time Invariant ◽  
Time Invariant ◽  
Time Periodic

The guaranteed simultaneous stabilization of two linear time-invariant plants is achieved by continuous-time periodic controller with high controller frequency. Simultaneous stabilization is accomplished by means of pole-placement along with robust zero error tracking to either of two plants. The present work also proposes an efficient design methodology for the same. The periodic controller designed and synthesized for realizable bounded control input with the proposed methodology is always possible to implement with guaranteed simultaneous stabilization for two plants. Simulation and experimental results establish the veracity of the claim.

Low Power Transposed Form 4-Tap Finite Impulse Response Filter using Power Efficient Multiply Accumulate Unit

2021 ◽  
pp. 2250016
Author(s):  
S. Rakesh ◽  
K. S. Vijula Grace
Keyword(s):  
Low Power ◽  
Impulse Response ◽  
Speech Processing ◽  
Video Processing ◽  
Filter Design ◽  
Finite Impulse Response ◽  
Low Power Design ◽  
Fir Filter ◽  
Efficient Design ◽  
Power Efficient

Finite impulse response (FIR) filters find wide application in signal processing applications on account of the stability and linear phase response of the filter. These digital filters are used in applications, like biomedical engineering, wireless communication, image processing, speech processing, digital audio and video processing. Low power design of FIR filter is one of the major constraints that researchers are trying hard to achieve. This paper presents the implementation of a novel power efficient design of a 4-tap 16-bit FIR filter using a modified Vedic multiplier (MVM) and a modified Han Carlson adder (MHCA). The units are coded using Verilog hardware description language and simulated using Xilinx Vivado Design Suite 2015.2. The filter is synthesized for the 7-series Artix field programmable gate array with xc7a100tcsg324-1 as the target device. The proposed filter design showed an improvement of a maximum of 57.44% and a minimum of 2.44% in the power consumption compared to the existing models.

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