Demonstration of Shor’s factoring algorithm for N $$=$$ 21 on IBM quantum processors

We report a proof-of-concept demonstration of a quantum order-finding algorithm for factoring the integer 21. Our demonstration involves the use of a compiled version of the quantum phase estimation routine, and builds upon a previous demonstration. We go beyond this work by using a configuration of approximate Toffoli gates with residual phase shifts, which preserves the functional correctness and allows us to achieve a complete factoring of $$N=21$$ N = 21 . We implemented the algorithm on IBM quantum processors using only five qubits and successfully verified the presence of entanglement between the control and work register qubits, which is a necessary condition for the algorithm’s speedup in general. The techniques we employ may be useful in carrying out Shor’s algorithm for larger integers, or other algorithms in systems with a limited number of noisy qubits.

Post-Synthesis Optimization of Reversible Circuits

One of the main motivations for reversible computing is that quantum computing has as one of its foundations the reversibility of all gates, that is, quantum computing circuit models are reversible. An important problem in reversible computing that has been intensively studied for the last decades is the synthesis of reversible circuits. The extended abstract considers optimization rules aiming to a new algorithm for post-synthesis optimization of reversible circuits composed of generalized Toffoli gates.

Editorial

Welcome to the sixth issue in 2021. I am very pleased to announce the journals’ Scopus CiteScore of 2.0 for 2020 indicating another scientifically successful year. On behalf of the J.UCS team, I would like to thank all authors for their sound research contributions, the reviewers for their very helpful suggestions and the consortium members for their financial support. Your commitment and dedicated work have strongly contributed to the long-lasting success of our journal. In this regular issue, I am very pleased to introduce five accepted papers from six different countries and 17 involved authors. Edinelço Dalcumune, Luis Antonio Brasil Kowada, André da Cunha Ribeiro, Celina Miraglia Herrera de Figueiredo and Franklin de Lima Marquezino from Brazil present in their article a new algorithm for synthesis of reversible circuits for arbitrary n-bit bijective functions using generalized Toffoli gates, which include positive and negative controls. Murat Firat, Derya Yiltas-Kaplan and Ruya Samli introduce their work on a machine learning method - including Artificial Neural Network (ANN), Linear Regression (LR) and Gradient Boosting (GB) - for determining optimal seat capacity that can supply the highest load factor for the flight operation between any two countries. In a collaborative research between Switzerland, China and the Netherlands Fabian Honegger, Yuan Feng and Matthias Rauterberg have investigated in their research effects of visual, auditory, vibration and draught stimuli on the sense of presence. Julio Moreno, David G. Rosado, Luis E. Sánchez, Manuel A. Serrano and Eduardo Fernández-Medina from Spain discuss in their research a security reference architecture for cyber-physical systems. Adem Tuncer from Turkey introduces a new approach based on a Artificial Bee Colony Algorithm for solving the 15-puzzle problem.

A reversible circuit synthesis algorithm with progressive increase of controls in generalized Toffoli gates

We present a new algorithm for synthesis of reversible circuits for arbitrary n-bit bijective functions. This algorithm uses generalized Toffoli gates, which include positive and negative controls. Our algorithm is divided into two parts. First, we use partially controlled gen- eralized Toffoli gates, progressively increasing the number of controls. Second, exploring the properties of the representation of permutations in disjoint cycles, we apply generalized Toffoli gates with controls on all lines except for the target line. Therefore, new in the method is the fact that the obtained circuits use first low cost gates and consider increasing costs towards the end of the synthesis. In addition, we employ two bidirectional synthesis strategies to improve the gate count, which is the metric used to compare the results obtained by our algorithm with the results presented in the literature. Accordingly, our experimental results consider all 3-bit bijective functions and twenty widely used benchmark functions. The results obtained by our synthesis algorithm are competitive when compared with the best results known in the literature, considering as a complexity metric just the number of gates, as done by alternative best heuristics found in the literature. For example, for all 3-bit bijective functions using generalized Toffoli gates library, we obtained the best so far average count of 5.23.

Quantum Circuit Design of Toom 3-Way Multiplication

In classical computation, Toom–Cook is one of the multiplication methods for large numbers which offers faster execution time compared to other algorithms such as schoolbook and Karatsuba multiplication. For the use in quantum computation, prior work considered the Toom-2.5 variant rather than the classically faster and more prominent Toom-3, primarily to avoid the nontrivial division operations inherent in the latter circuit. In this paper, we investigate the quantum circuit for Toom-3 multiplication, which is expected to give an asymptotically lower depth than the Toom-2.5 circuit. In particular, we designed the corresponding quantum circuit and adopted the sequence proposed by Bodrato to yield a lower number of operations, especially in terms of nontrivial division, which is reduced to only one exact division by 3 circuit per iteration. Moreover, to further minimize the cost of the remaining division, we utilize the unique property of the particular division circuit, replacing it with a constant multiplication by reciprocal circuit and the corresponding swap operations. Our numerical analysis shows that the resulting circuit indeed gives a lower asymptotic complexity in terms of Toffoli depth and qubit count compared to Toom-2.5 but with a large number of Toffoli gates that mainly come from realizing the division operation.

FPGA Implementation of Fault Tolerant & High Speed Reversible Systolic Multiplier

Multiplier is one of the essential components in the digital world such as in digital signal processing, quantum computing, microprocessor and widely used in arithmetic unit. The Reversible rationale is a used to decrease heat scattering and data misfortune. Contrasted with all essential math activities, multiplication requests all the more preparing time and look for complex equipment. This paper presents a plan of low power Systolic Array Multiplier utilizing Reversible logic gates which performs information handling in parallel. In this paper, we present a high speed 4x4 Systolic Multiplier design by using peres gate and toffoli gates and source code written in verilog and also implemented on FPGA Spartan 3s50pq208-4. The synthesis and simulation is done on Xilinx ISE 14.7. The delay is 17.642ns and static power dissipation is 24mW.