CICERO: A Domain-Specific Architecture for Efficient Regular Expression Matching

Regular Expression (RE) matching is a computational kernel used in several applications. Since RE complexity and data volumes are steadily increasing, hardware acceleration is gaining attention also for this problem. Existing approaches have limited flexibility as they require a different implementation for each RE. On the other hand, it is complex to map efficient RE representations like non-deterministic finite-state automata onto software-programmable engines or parallel architectures. In this work, we present CICERO , an end-to-end framework composed of a domain-specific architecture and a companion compilation framework for RE matching. Our solution is suitable for many applications, such as genomics/proteomics and natural language processing. CICERO aims at exploiting the intrinsic parallelism of non-deterministic representations of the REs. CICERO can trade-off accelerators’ efficiency and processors’ flexibility thanks to its programmable architecture and the compilation framework. We implemented CICERO prototypes on embedded FPGA achieving up to 28.6× and 20.8× more energy efficiency than embedded and mainstream processors, respectively. Since it is a programmable architecture, it can be implemented as a custom ASIC that is orders of magnitude more energy-efficient than mainstream processors.

Assessing the quality of intelligent systems with flexible programmable architecture

The purpose of this work is to assess the quality of functioning intelligent systems. Tasks to be solved: synthesis of an intelligent system based on unified modules, system quality assessment, system reconfiguration at a quality decrease. The research method is system analysis. A new flexible programmable architecture of intelligent systems has been developed. The flexible architecture of an intelligent system allows you to change the mutual relationships between subsystems, components and modules. The intelligent system is implemented on the basis of the unified modules that contain programmable switches. Switches are connected to the system inputs and outputs and are networked to transmit information.

Distributed image processing based on the same IP-cores in FPGA-architecture

The problem of processing images, i. e., two-dimensional data arrays, was solved through implementing two-dimensional fast Fourier transform (FFT) when using single-type hardware modules – IP-cores in the Virtex-6 FPGA architecture. We have shown the possibility of the parallel implementation of each stage in the two-dimensional FFT, based on four “butterfly”-type transforms (BTr) over four elements of the data array being processed. Estimations were obtained regarding time- and hardware complexity of the IPcore implementing BTrs and used in implementing the one-dimensional FFT. The results obtained can be used in estimating hardware and time consumption when performing a twodimensional FFT over an array of the pre-defined dimensionality in using existing and forthcoming distributed programmable-architecture systems.