Analog-to-digital converter (ADC) is one of the key component in any of the application oriented system design. This paper mainly focused on the simulation of various non-ideal parameters of an ADC as the number of resolution increases. The effect of non-ideal aspects like Jitter model and error block model are created in Matlab Simulink and the results are plotted. The dynamic non-ideal characteristics are discussed with their mathematical models and are compared with the equivalent resolution ADCs. The preliminary observations are also drawn according to the ideal characteristics. This shows that as the resolution increases, the bandwidth of non-ideal characteristics are also increases. This work is entitled to prove the non-idealities of 12-bit Pipeline ADC.
Photon-Detection Timing-Jitter Model in Verilog-A
