A dynamic jitter model to evaluate uncertainty trends with technology scaling

Abstract With technology scaling of semiconductor devices and further growth of the integrated circuit (IC) design and function complexity, it is necessary to increase the number of transistors in IC’s chip, layer stacks, and process steps. The last few metal layers of Back End Of Line (BEOL) are usually very thick metal lines (>4μm thickness) and protected with hard Silicon Dioxide (SiO2) material that is formed from (TetraEthyl OrthoSilicate) TEOS as Inter-Metal Dielectric (IMD). In order to perform physical failure analysis (PFA) on the logic or memory, the top thick metal layers must be removed. It is time-consuming to deprocess those thick metal and IMD layers using conventional PFA workflows. In this paper, the Fast Laser Deprocessing Technique (FLDT) is proposed to remove the BEOL thick and stubborn metal layers for memory PFA. The proposed FLDT is a cost-effective and quick way to deprocess a sample for defect identification in PFA.

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Nuclear energy. Nuclear fuel technology. Scaling factor method to determine the radioactivity of low and intermediate-level radioactive waste packages generated at nuclear power plants

10.3403/30118990 ◽

2007 ◽

Keyword(s):

Radioactive Waste ◽

Nuclear Fuel ◽

Nuclear Power ◽

Power Plants ◽

Nuclear Energy ◽

Scaling Factor ◽

Intermediate Level ◽

Technology Scaling ◽

Intermediate Level Radioactive Waste ◽

Fuel Technology

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DeepScaleTool : A Tool for the Accurate Estimation of Technology Scaling in the Deep-Submicron Era

2021 IEEE International Symposium on Circuits and Systems (ISCAS) ◽

10.1109/iscas51556.2021.9401196 ◽

2021 ◽

Author(s):

Satyabrata Sarangi ◽

Bevan Baas

Keyword(s):

Deep Submicron ◽

Accurate Estimation ◽

Technology Scaling

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Logic Technology Scaling: Present and Future

2021 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) ◽

10.1109/vlsi-tsa51926.2021.9440131 ◽

2021 ◽

Keyword(s):

Technology Scaling

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Reliability of Metal Gate / High-k devices and its impact on CMOS technology scaling

MRS Advances ◽

10.1557/adv.2017.504 ◽

2017 ◽

Vol 2 (52) ◽

pp. 2973-2982 ◽

Cited By ~ 2

Author(s):

Andreas Kerber

Keyword(s):

Dielectric Breakdown ◽

Cmos Technology ◽

Gate Stack ◽

Leakage Currents ◽

Technology Scaling ◽

Device Scaling ◽

Novel Device ◽

Time Dependent Dielectric Breakdown ◽

Bias Temperature Instability ◽

High K

ABSTRACTMG/HK was introduced into CMOS technology and enabled scaling beyond the 45/32nm technology node. The change in gate stack from poly-Si/SiON to MG/HK introduced new reliability challenges like the positive bias temperature instability (PBTI) and stress induced leakage currents (SILC) in nFET devices which prompted thorough investigation to provide fundamental understanding of these degradation mechanisms and are nowadays well understood. The shift to a dual-layer gate stack also had a profound impact on the time dependent dielectric breakdown (TDDB) introducing a strong polarity dependence in the model parameter. As device scaling continues, stochastic modeling of variability, both at time zero and post stress due to BTI, becomes critical especially for SRAM circuit aging. As we migrate towards novel device architectures like bulk FinFET, SOI FinFETs, FDSOI and gate-all-around devices, impact of self-heating needs to be accounted for in reliability testing.In this paper we summarize the fundamentals of MG/HK reliability and discuss the reliability and characterization challenges related to the scaling of future CMOS technologies.

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Effect of Technology Scaling on MOS Transistor Performance with High-K Gate Dielectrics

MRS Proceedings ◽

10.1557/proc-716-b3.3 ◽

2002 ◽

Vol 716 ◽

Author(s):

Nihar R. Mohapatra ◽

Madhav P. Desai ◽

Siva G. Narendra ◽

V. Ramgopal Rao

Keyword(s):

Gate Dielectric ◽

Gate Dielectrics ◽

Channel Length ◽

Mos Transistors ◽

Short Channel ◽

Technology Scaling ◽

Mos Transistor ◽

Wide Range ◽

Impact Of Technology ◽

The Impact

AbstractThe impact of technology scaling on the MOS transistor performance is studied over a wide range of dielectric permittivities using two-dimensional (2-D) device simulations. It is found that the device short channel performance is degraded with increase in the dielectric permittivity due to an increase in dielectric physical thickness to channel length ratio. For Kgate greater than Ksi, we observe a substantial coupling between source and drain regions through the gate dielectric. We provide extensive 2-D device simulation results to prove this point. Since much of the coupling between source and drain occurs through the gate dielectric, it is observed that the overlap length is an important parameter for optimizing DC performance in the short channel MOS transistors. The effect of stacked gate dielectric and spacer dielectric on the MOS transistor performance is also studied to substantiate the above observations.

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Energy Efficient VLSI Based DCT Architecture with Accurate Error Compensation

Applied Mechanics and Materials ◽

10.4028/www.scientific.net/amm.626.127 ◽

2014 ◽

Vol 626 ◽

pp. 127-135 ◽

Cited By ~ 1

Author(s):

D. Jessintha ◽

M. Kannan ◽

P.L. Srinivasan

Keyword(s):

Low Power ◽

Energy Efficient ◽

Time Complexity ◽

High Performance ◽

Low Power Consumption ◽

Distributed Arithmetic ◽

Technology Scaling ◽

Truncation Errors ◽

History Of ◽

Technology Dependency

Discrete Cosine Transform (DCT) is commonly used in image compression. In the history of DCT, a milestone was the Distributed Arithmetic (DA) technique. Due to the technology dependency a multiplier-less computation was built with DA based technique. It occupied less area but the throughput is less. Later, due to the technology scaling, multiplier based architectures can be easily adapted for low-power and high-performance architecture. Fixed width multipliers [1]-[7] reduces hardware and time complexity. In this work, Radix 4 fixed width multiplier is adapted with DCT architecture due to low power consumption and saves 30% power. In order to reduce truncation errors caused during fixed width multiplication, an estimation circuit is designed based on conditional probability theory.

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