Design of Low-Noise Two-Path Amplifier for 6–16 GHz Applications

A two-path low-noise amplifier (LNA) is designed with TSMC 0.18[Formula: see text][Formula: see text]m standard RF CMOS process for 6–16[Formula: see text]GHz frequency band applications. The principle of a conventional resistive shunt feedback LNA is analyzed to demonstrate the trade-off between the noise figure (NF) and the input matching. To alleviate the mentioned issue for wideband application, this structure with noise canceling technique and linearity improvement are applied to a two-path structure. Flat and high gain is supplied by the primary path; while the input and output impedance matching are provided by the secondary path. The [Formula: see text][Formula: see text]dB bandwidth can be increased to a higher frequency by inductive peaking, which is used at the first stage of the two paths. Besides, by biasing the transistors at the threshold voltage, low power dissipation is achieved. The [Formula: see text][Formula: see text]dB gain bandwidth of the proposed LNA is 10[Formula: see text]GHz, while the maximum power gain of 13.1[Formula: see text]dB is attained. With this structure, minimum NF of 4.6[Formula: see text]dB and noise flatness of 1[Formula: see text]dB in the whole bandwidth can be achieved. The input impedance is matched, and S[Formula: see text] is lower than [Formula: see text]10 dB. With the proposed linearized LNA, the average IIP[Formula: see text][Formula: see text]dBm is gained, while it occupies 1051.7[Formula: see text][Formula: see text]m die area.

Linearity Improvement of Bulk Driven Floating Gate OTA Using Cross-Bulk and Quasi-Bulk Techniques

In this paper, two highly linear OTAs are presented using a combination of three linearization techniques: floating gate, bulk driven, and source degeneration. In the first OTA, bulk driven floating gate MOSFETs are used as input transistors. The input signal given at the bulk terminals of these input transistors are in the opposite phase of the input signal provided to one of the gates of the respective floating gate MOSFET. This cross-coupling method resulted in a highly linear voltage-to-current conversion at the cost of reduced transconductance. In the second proposed OTA, this reduction in transconductance is restored by using novel quasi-bulk floating gate MOSFETs as input transistors while maintaining the improved linearity. Both the OTAs are designed and simulated using 180 nm CMOS design library and powered with [Formula: see text]0.5[Formula: see text]V dual power supply. The process variation and mismatch effects on both the OTAs are examined using corner and Monte Carlo analysis. The layouts of the proposed OTAs are also presented and workability is confirmed using post-layout simulations.

Comparison of Neutron-Gamma Separation Qualities of Various Organic Scintillation Materials and Liquid Scintillator LSB-200

In this work, we compare the pulse-shape discrimination (PSD) properties of newly developed liquid scintillator LSB-200, EJ-299-33A, BC-501A, stilbene, p-terphenyl, and Hidex Aqualight in neutron field generated by the LVR-15 reactor with silicon filter utilization. Pulses from the scintillators are processed by the Neutron-Gamma spectrometer. This spectrometric system with fast digitizer card contains two analog–digital converters with a resolution of 12 bits and sampling frequency 500 × 106 Hz. For photomultiplier linearity improvement, the active divider has been used. Measured data from scintillators have been processed using the integration method and compared. The results are presented.

Fixed Pattern Noise Reduction and Linearity Improvement in Time-Mode CMOS Image Sensors

In the paper, a digital clock stopping technique for gain and offset correction in time-mode analog-to-digital converters (ADCs) has been proposed. The technique is dedicated to imagers with massively parallel image acquisition working in the time mode where compensation of dark signal non-uniformity (DSNU) as well as photo-response non-uniformity (PRNU) is critical. Fixed pattern noise (FPN) reduction has been experimentally validated using 128-pixel CMOS imager. The reduction of the PRNU to about 0.5 LSB has been achieved. Linearity improvement technique has also been proposed, which allows for integral nonlinearity (INL) reduction to about 0.5 LSB. Measurements confirm the proposed approach.