Fine-grained magnetoelectric Sr0.5Ba0.5Nb2O6–CoFe2O4 composites synthesized by a straightforward one-pot method

Magnetoelectric (Sr0.5Ba0.5Nb2O6)1x(CoFe2O4)x (x = 0.2–0.6) composites were prepared by a one-pot softchemistrysynthesis using PEG400. Calcining at 700 ◦C resulted in nanocrystalline composite powders (dcryst. =24–30 nm) which were sintered between 1050 and 1200 ◦C to ceramic bodies with relative densities up to 98%.SEM investigations confirm the formation of composite ceramics with a 0–3 connectivity and variable grain sizesfrom 0.2 to 3.6 μm for sintering up to 1150 ◦C, while sintering at 1200 ◦C leads both to a change in themicrostructure and a considerable grain growth. Magnetic measurements at 300 K reveal ferrimagnetic behaviourwith saturation magnetization values smaller than bulk CoFe2O4 and coercivities between 790 and 160 Oe.Temperature-dependent impedance spectroscopy showed that the relative permittivities decrease both withrising frequency and CoFe2O4 fraction. The frequency dependence of the impedance can be well described usinga single RC circuit. Magnetoelectric measurements show the presence of pronounced field hystereses. Themaximum magnetoelectric coefficient (αME) depends both on the CoFe2O4 fraction (x) and sintering temperature.The composite with x = 0.3 exhibits the largest αME value of 37 μV Oe1 cm1 (@ 900 Hz). With rising frequencyof the AC driving field αME increases up to 300–400 Hz and is nearly constant until 1 kHz.

Application of RC delay time for estimation of thermal properties

The analogy between the electrical and thermal system has been extensively used to solve different kinds of direct heat transfer problems. However, this analogy has not been explored much to obtain solutions of inverse heat transfer problems like estimation of thermal properties. This paper presents an approach of estimation of thermal properties using the correspondence between the thermal and electrical domains by exploiting the concept of RC delay time in the resistance-capacitance (RC) circuit. Simulations and experiments have been performed on stainless steel and glass samples to show the applicability of the proposed approach for materials belonging to different conductivity range.

On-chip interconnects modeling and timing driven buffer insertion

With the increasing effect of on-chip interconnects on nowadays [sic] VLSI design performance, modeling of interconnects becomes a necessity. GAM, TPN, and AWE are well known methods that are used to map an interconnect to an equivalent electrical circuit. In this thesis, a general approach that considers z-parameters is developed witch allows the generation of equivalent RC, RLC, and RLCG circuits for both T and ∏ configurations. The performance of these generated circuits is compared to H-spice simulations by measuring the effect of interconnects on the transition times and delays under different conditions such as input transition times, interconnect lengths and capacitive loads. As a result, the a-configuration of AWE method reveals consistently an acceptable performance which makes it a good candidate to be utilized for buffer insertion.Buffer insertion is a popular technique used to reduce the delay of a long interconnect by segmenting it and inserting buffers among these segments. Therefore, the performance of this technique depends strongly on the accuracy of the considered interconnect model. However, using a model such as the RLCG of ∏ configuration which is derived from using the AWE method is not practical due to the complexity accompanied by such model which makes the derivation of closed-form expressions very complicated. To overcome this dilemma, the selected configuration has been mapped to a simple equivalent RC circuit. As a consequence, a new RC representation of on-chip interconnects is developed. Moreover, depending on the developed RC model, the proposed buffer insertion technique shows superiority over previously published works.

On-chip interconnects modeling and timing driven buffer insertion

With the increasing effect of on-chip interconnects on nowadays [sic] VLSI design performance, modeling of interconnects becomes a necessity. GAM, TPN, and AWE are well known methods that are used to map an interconnect to an equivalent electrical circuit. In this thesis, a general approach that considers z-parameters is developed witch allows the generation of equivalent RC, RLC, and RLCG circuits for both T and ∏ configurations. The performance of these generated circuits is compared to H-spice simulations by measuring the effect of interconnects on the transition times and delays under different conditions such as input transition times, interconnect lengths and capacitive loads. As a result, the a-configuration of AWE method reveals consistently an acceptable performance which makes it a good candidate to be utilized for buffer insertion.Buffer insertion is a popular technique used to reduce the delay of a long interconnect by segmenting it and inserting buffers among these segments. Therefore, the performance of this technique depends strongly on the accuracy of the considered interconnect model. However, using a model such as the RLCG of ∏ configuration which is derived from using the AWE method is not practical due to the complexity accompanied by such model which makes the derivation of closed-form expressions very complicated. To overcome this dilemma, the selected configuration has been mapped to a simple equivalent RC circuit. As a consequence, a new RC representation of on-chip interconnects is developed. Moreover, depending on the developed RC model, the proposed buffer insertion technique shows superiority over previously published works.

Convolution Integral: How a Graphical Type of Solution Can Help Minimize Misconceptions

A physical system, Low Pass Filter (LPF) RC Circuit, which serves as an impulse response and a square wave input signal are utilized to derive the continuous time convolution (convolution integrals). How to set up the limits of integration correctly and how the excitation source convolves with the impulse response are explained using a graphical type of solution. This in turn, help minimize the students’ misconceptions about the convolution integral. Further, the effect of varying the circuit elements on the shape of the convolution output plot is presented allowing students to see the connection between a convolution integral and a physical system. PSpice simulation and experiment results are incorporated and are compared with those of the analytical solution associated with the convolution integral.