Frequency dependence on polarization switching measurement in ferroelectric capacitors

Ferroelectric hysteresis loop measurement under high driving frequency generally faces great challenges. Parasitic factors in testing circuits such as leakage current and RC delay could result in abnormal hysteresis loops with erroneous remnant polarization (P r) and coercive field (E c). In this study, positive-up-negative-down (PUND) measurement under a wide frequency range was performed on a 10-nm thick Hf0.5Zr0.5O2 ferroelectric film. Detailed analysis on the leakage current and RC delay was conducted as the polarization switching occurs in the FE capacitor. After considering the time lag caused by RC delay, reasonable calibration of current response over the voltage pulse stimulus was employed in the integral of polarization current over time. In such a method, rational P–V loops measured at high frequencies (>1 MHz) was successfully achieved. This work provides a comprehensive understanding on the effect of parasitic factors on the polarization switching behavior of FE films.

Application of RC delay time for estimation of thermal properties

The analogy between the electrical and thermal system has been extensively used to solve different kinds of direct heat transfer problems. However, this analogy has not been explored much to obtain solutions of inverse heat transfer problems like estimation of thermal properties. This paper presents an approach of estimation of thermal properties using the correspondence between the thermal and electrical domains by exploiting the concept of RC delay time in the resistance-capacitance (RC) circuit. Simulations and experiments have been performed on stainless steel and glass samples to show the applicability of the proposed approach for materials belonging to different conductivity range.

Gate-All-Around FETs: Nanowire and Nanosheet Structure

DC/AC performances of 3-nm-node gate-all-around (GAA) FETs having different widths and the number of channels (Nch) from 1 to 5 were investigated thoroughly using fully-calibrated TCAD. There are two types of GAAFETs: nanowire (NW) FETs having the same width (WNW) and thickness of the channels, and nanosheet (NS) FETs having wide width (WNS) but the fixed thickness of the channels as 5 nm. Compared to FinFETs, GAAFETs can maintain good short channel characteristics as the WNW is smaller than 9 nm but irrespective of the WNS. DC performances of the GAAFETs improve as the Nch increases but at decreasing rate because of the parasitic resistances at the source/drain epi. On the other hand, gate capacitances of the GAAFETs increase constantly as the Nch increases. Therefore, the GAAFETs have minimum RC delay at the Nch near 3. For low power applications, NWFETs outperform FinFETs and NSFETs due to their excellent short channel characteristics by 2-D structural confinement. For standard and high performance applications, NSFETs outperform FinFETs and NWFETs by showing superior DC performances arising from larger effective widths per footprint. Overall, GAAFETs are great candidates to substitute FinFETs in the 3-nm technology node for all the applications.

Analysis of Organic Light-Emitting Diode SPICE Models with Constant or Voltage-Dependent Components

A simplified OLED SPICE model with two resistors and two capacitors that have constant or voltagedependent (VD) values is proposed. Our model includes physical characteristics such as voltage and frequency dependency and agrees well with measurements. In this paper, we analyze the OLED frequency dependency effects and RC delay properties by controlling model parameters for DC, AC, and transient conditions. Importantly, we found that a model with constant parameters is simple and is accurate enough. Based on our simulation results, we suggest a new guideline for an OLED SPICE circuit model and simulation target.

Intra-Chip and Inter-Chip Wireless Communication Analysis for Millimeter Wave using Miniaturized On-Chip Antenna

System on Chip (SoC) is an emerging technology for semiconductor devices that aims for better compaction with reduced interconnects, RC delay, noise, and power consumption. Wired connections between chips, ICs or SoC’s lead to increased heat dissipation, which is undesirable. Hence, mechanisms have been developed for making communication between the chips wireless and use of miniaturized RF antenna is inevitable. In this paper, to analyse the performance of wireless communication over millimeter range, millimeter scale RF antennas operating at frequencies of 20 GHz to 70 GHz are considered. Using ANSYS HFSS software, the scenario for intra and inter chip wireless communication is established using the bowtie antenna operating around 50 GHz and their performance evaluation is done considering the various parameters. An intrachip system of four bowtie antennas is simulated around 50GHz and the S-parameters are plotted and analysed