The Testable Design | ScienceGate

Testable design for cell-based design ASICs and its application to VLSI image signal processor

Electronics and Communications in Japan (Part III Fundamental Electronic Science) ◽

10.1002/ecjc.4430760406 ◽

1993 ◽

Vol 76 (4) ◽

pp. 47-56

Author(s):

Hiroyuki Kawai ◽

Shin-Ichi Nakagawa ◽

Masahiko Yoshimoto ◽

Yasutaka Horiba ◽

Takuji Ogihara ◽

...

Keyword(s):

Image Signal Processor ◽

Testable Design ◽

Signal Processor

Testable design of large random access memories

Integration ◽

10.1016/0167-9260(84)90030-0 ◽

1984 ◽

Vol 2 (4) ◽

pp. 309-330 ◽

Cited By ~ 7

Author(s):

Kewal K. Saluja ◽

Kim Thang Le

Keyword(s):

Random Access ◽

Testable Design

A testable design of logic circuits under highly observable condition

Proceedings. International Test Conference 1990 ◽

10.1109/test.1990.114116 ◽

2002 ◽

Cited By ~ 5

Author(s):

W. Xiaoqing ◽

K. Kinoshita

Keyword(s):

Logic Circuits ◽

Testable Design

Delay Testable Design Using Modified Boundary Scan

Journal of The Japan Institute of Electronics Packaging ◽

10.5104/jiep.24.663 ◽

2021 ◽

Vol 24 (7) ◽

pp. 663-667

Author(s):

Hiroyuki Yotsuyanagi ◽

Masaki Hashizume

Keyword(s):

Boundary Scan ◽

Testable Design

Testable design of multiple-stage OTA-C filters

IEEE Transactions on Instrumentation and Measurement ◽

10.1109/19.872910 ◽

2000 ◽

Vol 49 (5) ◽

pp. 929-934 ◽

Cited By ~ 5

Author(s):

Cheng-Chung Hsu ◽

Wu-Shiung Feng

Keyword(s):

Testable Design

Macro-test: a VLSI testable-design technique

Algorithmic and Knowledge-based CAD for VLSI ◽

10.1049/pbcs004e_ch9 ◽

2011 ◽

pp. 180-200

Author(s):

F. Beenker ◽

R. Bennetts

Keyword(s):

Design Technique ◽

Testable Design

Method for testable design and for built-in test

[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design ◽

10.1109/isvd.1991.185136 ◽

1991 ◽

Author(s):

P.G. Petrov

Keyword(s):

Testable Design

Testable design of two-dimensional cellular logic arrays for detecting stuck-at and bridging faults

Computers & Electrical Engineering ◽

10.1016/0045-7906(88)90011-0 ◽

1988 ◽

Vol 14 (3-4) ◽

pp. 65-74

Author(s):

Bidyut Gupta ◽

Bhargab B. Bhattacharya ◽

Gopal C. Basu

Keyword(s):

Two Dimensional ◽

Bridging Faults ◽

Cellular Logic ◽

Testable Design

The influences of fault type and topology on fault model performance and the implications to test and testable design

27th ACM/IEEE Design Automation Conference ◽

10.1145/123186.123436 ◽

1990 ◽

Cited By ~ 2

Author(s):

Kenneth M. Butler ◽

M. Ray Mercer

Keyword(s):

Model Performance ◽

Fault Model ◽

Fault Type ◽

And Topology ◽

Testable Design

Digital Systems : Testing and Testable Design

European Journal of Operational Research ◽

10.1016/0377-2217(90)90290-r ◽

1990 ◽

Vol 47 (2) ◽

pp. 265

Keyword(s):

Digital Systems ◽

Testable Design