Development of the technology of systems on a chip for a modern electronic component base ECB

Without the creation of Russian technology for designing SoC, it is impossible to provide a modern level of VLSI development, both for defense and civil applications. This is in line with global development trends. Nevertheless, it is necessary to highlight only those essential processes that are most consistent with Russian realities and can help in solving specific problems of the defense industry and the economy as a whole at the lowest cost and in the shortest possible time. The most important element of the implementation of SoC technology is the organization of a single sign-on to locate the production of microcircuits based on this technology. This will allow to drastically reduce costs, to certify the system of complex functional blocks, to increase the reliability and sustainability of developments. Even in organizational terms, this will allow an organized firm (conditionally - Silicon Gate) to be included as a certified chip manufacturer in any contracts with MO. The article discusses the structuring of programs for the development of domestic technology of SoC systems on a chip, the coordination of the SoC area of developments and complex functional blocks, as well as their information support.

Secure acceleration on cloud-based FPGAs – FPGA enclaves

FPGAs are becoming a common sight in cloud<br>environments and new usage paradigms, such as FPGA-as-a-Service, have emerged. This development poses a challenge to traditional FPGA security models, as these are assuming trust between the user and the hardware owner. Currently, the user cannot keep bitstream nor data protected from the hardware owner in an FPGA-as-a-service setting. This paper proposes a security model where the chip manufacturer takes the role of root-of-trust to remedy these security problems. We suggest that the chip manufacturer creates a Public Key Infrastructure (PKI), used for user bitstream protection and data encryption, on each device. The chip manufacturer, rather than the hardware owner,<br>also controls certain security-related peripherals. This allows the user to take control over a predefined part of the programmable logic and set up a protected enclave area. Hence, all user data can be provided in encrypted form and only be revealed inside the enclave area. In addition, our model enables secure and concurrent multi-tenant usage of remote FPGAs. To also consider the needs of the hardware owner, our solution includes bitstream certification and affirming that uploaded bitstreams have been vetted against maliciousness.

Secure acceleration on cloud-based FPGAs – FPGA enclaves

FPGAs are becoming a common sight in cloud<br>environments and new usage paradigms, such as FPGA-as-a-Service, have emerged. This development poses a challenge to traditional FPGA security models, as these are assuming trust between the user and the hardware owner. Currently, the user cannot keep bitstream nor data protected from the hardware owner in an FPGA-as-a-service setting. This paper proposes a security model where the chip manufacturer takes the role of root-of-trust to remedy these security problems. We suggest that the chip manufacturer creates a Public Key Infrastructure (PKI), used for user bitstream protection and data encryption, on each device. The chip manufacturer, rather than the hardware owner,<br>also controls certain security-related peripherals. This allows the user to take control over a predefined part of the programmable logic and set up a protected enclave area. Hence, all user data can be provided in encrypted form and only be revealed inside the enclave area. In addition, our model enables secure and concurrent multi-tenant usage of remote FPGAs. To also consider the needs of the hardware owner, our solution includes bitstream certification and affirming that uploaded bitstreams have been vetted against maliciousness.

Wingtech Acquires Nexperia: Will the New Company Fly?

This case is about Wingtech, a China-based mobile phone and intelligent devices manufacturer. Early in 2019, Wingtech CEO Xuezheng Zhang faced one of the biggest challenges of his career. Founded only 13 years earlier, Wingtech was one of the world’s top producers of high-tech consumer products. But Wingtech didn’t produce its products’ key component: microchips. Instead, the vast majority of chips were imported from American and European manufacturers. Facing growing hostility from an increasingly anti-China U.S., and the very real possibility of crippling disruptions to the microchip supply chain, Wingtech had just completed the purchase of highly regarded Netherlands-based chip manufacturer Nexperia for USD3.6 billion. Now Zhang faced a daunting set of highly consequential new questions. To what extent should he try to integrate the two geographically and culturally distinct companies? How could he convince Nexperia’s highly competent leader, who had been unenthusiastic about the deal, to stay? Zhang had seen great success as an entrepreneur. How should he lead as the CEO of a global high-tech firm?

An Empirical Analysis of Employee Responses to Bonuses and Penalties

ABSTRACT We examine how employees respond to bonuses and penalties using a proprietary dataset from an electronic chip manufacturer in China. First, we examine the relative effects of bonuses and penalties and observe a stronger effect on subsequent effort and performance for penalties than for bonuses. Second, we find that the marginal sensitivity of penalties diminishes faster than that of bonuses, indicating that the marginal effect of a bonus may eventually exceed that of a penalty as their value increases. Third, we find an undesirable selection effect of penalties: penalties increase employee turnover, especially for skillful and high-quality workers. These results may help inform our understanding of the observed limited use of penalties in practice due to their bounded effectiveness and possible unintended consequences. Data Availability: The confidentiality agreement with the company that provided data for this study precludes the dissemination of detailed data without the company's consent.

BEHAVIORAL MODEL OF A LINEAR VOLTAGE STABILIZER IN THE SPICE LANGUAGE

A variant of the implementation of the behavioral model of a linear voltage stabilizer in the Spice language is presented. The results of modeling in static mode are presented. The simulation results are compared with experimental data and technical description of the chip manufacturer.