Design and Analysis of CMOS Phase Lock Loop (PLL) Using VLSI Technology

This paper proffers comparative research of Complementary MOSFET (CMOS) of the Phase Lock Loop (PPL) circuit. Our approach is based on hybrid design Phase Lock Loop (PLL) circuits combined in a single unit. A phase-locked loop (PLL) is used in space communication for synchronization purposes also very useful in time to digital converters and in instrumentation engineering. A phased lock loop (PLL) is a control system that makes an output signal whose frequency depends on the input phase difference. The phase detector takes the phase of an input signal and compares it with the phase procured from its output oscillator regulates the frequency of its oscillator to manage the phase matches. Different techniques like analogue and digital simulation with the help of mathematical/logical connections are found in Research to create the Phase Locked Loop (PLL). This limitation can be overcome by replicating the circuit block whose supply voltage is being reduced to manage the same throughout. This paper includes design features for low power phase-locked loop using Very-large-scale integration (VLSI) technology. The signal from the phase detector controls the oscillator in a feedback loop. As such: an operational device the PLL has a wide range of applications in computers sciences, telecommunication, and electronic system applications; we aim to design and examine the phase lock loop circuit in multiple technologies and examine their power capacity. By using the hybrid structure of NMOS and PMOS, here we have achieved the circuit of Phase Lock Loop (PLL) using VLSI technology. Keywords: Technology, CMOS, Phase lock loop, Micro wind, Voltage control oscillator, VLSI technology.

Design and Performance Analysis of Low Power High Speed Adder and Multiplier Using MTCMOS in 90nm, 70nm, 25nm and 18nm Regime

Nowadays, VLSI technology mainly focused on High-Speed Propagation and Low Power Consumption. Addition is an important arithmetic operation which plays a major role in digital application. Adder is act as an important role in the applications of signal processing, in memory access address generation and Arithmetic Logic Unit. When the number of transistors increases in system designs, makes to increase power and complexity of the circuit. One of the dominant factors is power reduction in low power VLSI technology and to overcome the power dissipation in the existing adder circuit, MTCMOS technique is used in the proposed adder. The design is simulated in 90nm, 70nm, 25nm and 18nm technology and then comparison is made between existing and proposed system in the context of energy, area and delay. In this comparison, the efficiency metrics power and delay are found to be reduced 20% from the existing adder and the proposed adder is used for the design of low power multiplier.

Low Power Circuit Design for Footed Quasi Resistance Scheme In 45NM VLSI Technology

Low power has arisen as a chief topic in these days and hardware enterprises. Power dissipation has become a significant thought as execution and zone of VLSI Chip plan. In this paper, a design of low power for footed quasi resistance scheme in 45nanometer VLSI technology, using appropriate standard digital gates with 45nm technology, considering footed quasi resistance technique for nanoscales is introduced. Transition of logic 1 and 0 is the main problem in the cascading circuits, this problem can solved by employing a basic inverter called as Domino logic at output.Due to the precharge propagation the power dissipation is observed in domino logic, this will be resolved using PDB (Pseudo Dynamic Buffer) model. With the help of PDB nearly 67% of power saved. Even though PDB is succeeded in precharge propagation, it fails in logic transition, this may results erroneous output during cascading. With contracting technology, power utilization can decreased and over all power of the executives on chip are the critical difficulties below 100nm because of expanded intricacy. In this paper execution of low power circuit scheme for footed quasi resistance plot in 45nm VLSI technology. In this paper we will actualize and recreate low power circuit scheme for footed quasi resistance plot in 45nm VLSI technology.

An Investigation for the Negative-Bias Temperature Instability Aware CMOS Logic

Background: Scaling of the dimensions of semiconductor device plays a very important role in the advancement of very large-scale integration (VLSI) technology. There are many advantages of scaling in VLSI technology such as increment in the speed of the device and less area requirement of the device. Aggressive device scaling causes some limitations in the form of short channel effects which produce large leakage current. Large leakage current harms the characteristics of the device and affects the reliability of the device. Objective: The most important and popular reliability issue in deep submicron (DSM) regime is negative-bias temperature instability (NBTI). NBTI effect increases the threshold voltage of p-channel metal oxide semiconductor (PMOS) device over the time and affects the different characteristics of the device. As a result, circuit delay exceeds the design specification and there may be timing violations or logic failure. Different performance parameters are observed under NBTI effect for different logic gates. Methods: This paper presents an impact of NBTI at 22nm Berkeley short-channel IGFET model4 (BSIM4) predictive technology model (PTM) for complementary metal oxide semiconductor (CMOS) logic gates. Reliability simulations are utilised to evaluate the amount of gradual damage in PMOS device due to NBTI effect. Results : The impact of NBTI degradation is checked for various CMOS logic gates using Mentor Graphics’s Eldo circuit simulator. Output voltage and drain current are reducing over the time under NBTI effect. Conclusion: NBTI degradation increases the threshold voltage of PMOS device over the time and affects the different characteristics of the device.