Computing Performance Enhancement of VLIW Architecture Using Instruction Level Parallelism

Our paper proposes the new method of processor architecture called as VLIW for enhancing the performance of the architecture. VLIW is the complexity architecture because the enormous number of registers, slices, flip flops, counters, operand, ALUs, and MUXs used. The VLIW has the fife stages of pipelines for executing the architecture are (1) fetching the 128-bit instruction memory, (2) decode stage or it is also called as the operands reading stage because the total number of operands are implemented in this stage, (3) execution stage, here the operations with the parallel executions units which has the four operations, (4) memory stage is used for loading or for storing the data from/to the memory and (5) write back stage in this stage the outputs of all the stage is collected and write back into the register file for storing the output values. The whole process of implementation is implemented in the FPGA of the family of Spartan-6 XC6SLX-3CSG324 device. In this proposed architecture the performance of the architecture is increased by reducing the time taken to execute the CPU of Xst completion of the architecture

A Computational Design of a Programmable Biological Processor

Basic synthetic information processing structures, such as logic gates, oscillators and flip-flops, have already been implemented in living organisms. Current implementations of these structures are, however, hardly scalable and are yet to be extended to more complex processing structures that would constitute a biological computer.Herein, we make a step forward towards the construction of a biological computer. We describe a model-based computational design of a biological processor, composed of an instruction memory containing a biological program, a program counter that is used to address this memory and a biological oscillator that triggers the execution of the next instruction in the memory. The described processor uses transcription and translation resources of the host cell to perform its operations and is able to sequentially execute a set of instructions written within the so-called instruction memory implemented with non-volatile DNA sequences. The addressing of the instruction memory is achieved with a biological implementation of the Johnson counter, which increases its state after an instruction is executed. We additionally describe the implementation of a biological compiler that compiles a sequence of human-readable instructions into ordinary differential equations-based models. These models can be used to simulate the dynamics of the proposed processor.The proposed implementation presents the first programmable biological processor that exploits cellular resources to execute the specified instructions. We demonstrate the application of the proposed processor on a set of simple yet scalable biological programs. Biological descriptions of these programs can be written manually or can be generated automatically with the employment of the provided compiler.

Design and Implementation of Synthesizable 32-bit Four Stage Pipelined RISC Processor in FPGA Using Verilog/VHDL

This paper is delineating the design and implementation of high performance, synthesizable 32-bit pipelined Reduced Instruction Set Computer (RISC) Core. The design of the Harvard Architecture based 32-bit RISC Core involves design of 32-bit Data-path Unit, Control Unit, 32-bit Instruction Memory, 32-bit Data Memory, Register file with each register of size 32 bit. The processor is divided into Fetch, Decode, Execute and Write Back block in order to implement a four-stage pipeline. A 2*16 LCD is connected to the processor IO block to show the instruction execution sequence for demonstration in FPGA. The RISC Core is designed using Verilog HDL and VHDL and is tested in ISIM Simulator. The implementation of the processor is done in a Spartan 3E Starter Board using Xilinx ISE 14.7. All of the instructions incorporated with the processor have been tested successfully both in simulation and hardware implementation in FPGA.DOI: http://dx.doi.org/10.3126/njst.v15i1.12021 Nepal Journal of Science and TechnologyVol. 15, No.1 (2014) 81-88