Communications in Computer and Information Science - VLSI Design and Test
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Published By Springer Berlin Heidelberg

9783642420238, 9783642420245

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

10 Gbps Current Mode Logic I/O Buffer

Communications in Computer and Information Science - VLSI Design and Test ◽

10.1007/978-3-642-42024-5_8 ◽

2013 ◽

pp. 59-65

Author(s):

Akhil Rathore ◽

Chetan D Parikh

Keyword(s):

Current Mode ◽

Current Mode Logic

3D CORDIC Algorithm Based Cartesian to Spherical Coordinate Converter

Communications in Computer and Information Science - VLSI Design and Test ◽

10.1007/978-3-642-42024-5_40 ◽

2013 ◽

pp. 337-344

Author(s):

Anita Jain ◽

Kavita Khare

Keyword(s):

Cordic Algorithm ◽

Spherical Coordinate

Circuit Transient Analysis Using State Space Equations

Communications in Computer and Information Science - VLSI Design and Test ◽

10.1007/978-3-642-42024-5_39 ◽

2013 ◽

pp. 330-336

Author(s):

Kai Chi Alex Lam ◽

Mark Zwolinski

Keyword(s):

State Space ◽

Transient Analysis

Variation Robust Subthreshold SRAM Design with Ultra Low Power Consumption

Communications in Computer and Information Science - VLSI Design and Test ◽

10.1007/978-3-642-42024-5_29 ◽

2013 ◽

pp. 242-248 ◽

Cited By ~ 1

Author(s):

Saima Cherukat ◽

Vineet Sahula

Keyword(s):

Power Consumption ◽

Low Power ◽

Low Power Consumption ◽

Ultra Low Power ◽

Sram Design

CMOS ASIC Design of a High Performance Digital Fuzzy Processor That Can Compute on Arbitrary Membership Functions

Communications in Computer and Information Science - VLSI Design and Test ◽

10.1007/978-3-642-42024-5_28 ◽

2013 ◽

pp. 233-241 ◽

Cited By ~ 1

Author(s):

Anirban Guha ◽

Shubhajit Roy Chowdhury

Keyword(s):

High Performance ◽

Membership Functions ◽

Asic Design

Energy Efficient Array Initialization Using Loop Unrolling with Partial Gray Code Sequence

Communications in Computer and Information Science - VLSI Design and Test ◽

10.1007/978-3-642-42024-5_11 ◽

2013 ◽

pp. 83-93

Author(s):

Sumanta Pyne ◽

Ajit Pal

Keyword(s):

Energy Efficient ◽

Gray Code ◽

Code Sequence ◽

Loop Unrolling

Process Aware Ultra-High-Speed Hybrid Sensing Technique for Low Power Near-Threshold SRAM

Communications in Computer and Information Science - VLSI Design and Test ◽

10.1007/978-3-642-42024-5_1 ◽

2013 ◽

pp. 1-9

Author(s):

Bhupendra Singh Reniwal ◽

Santosh Kumar Vishvakarma

Keyword(s):

Low Power ◽

High Speed ◽

Ultra High Speed ◽

Near Threshold

A Dual Material Double-Layer Gate Stack Junctionless Transistor for Enhanced Analog Performance

Communications in Computer and Information Science - VLSI Design and Test ◽

10.1007/978-3-642-42024-5_15 ◽

2013 ◽

pp. 118-127 ◽

Cited By ~ 2

Author(s):

Ratul Kumar Baruah ◽

Roy P. Paily

Keyword(s):

Double Layer ◽

Gate Stack ◽

Analog Performance ◽

Junctionless Transistor ◽

Dual Material

Fault Aware Dynamic Adaptive Routing Using LBDR

Communications in Computer and Information Science - VLSI Design and Test ◽

10.1007/978-3-642-42024-5_36 ◽

2013 ◽

pp. 304-311

Author(s):

Rimpy Bishnoi ◽

Vijay Laxmi ◽

Manoj Singh Gaur ◽

Mohit Baskota

Keyword(s):

Adaptive Routing

On Designing Testable Reversible Circuits Using Gate Duplication

Communications in Computer and Information Science - VLSI Design and Test ◽

10.1007/978-3-642-42024-5_38 ◽

2013 ◽

pp. 322-329 ◽

Cited By ~ 6

Author(s):

Joyati Mondal ◽

Debesh Kumar Das ◽

Dipak Kole ◽

Hafizur Rahaman ◽

Bhargab B. Bhattacharya

Keyword(s):

Reversible Circuits

Communications in Computer and Information Science - VLSI Design and TestLatest Publications

TOTAL DOCUMENTS

H-INDEX

Published By Springer Berlin Heidelberg

10 Gbps Current Mode Logic I/O Buffer

3D CORDIC Algorithm Based Cartesian to Spherical Coordinate Converter

Circuit Transient Analysis Using State Space Equations

Variation Robust Subthreshold SRAM Design with Ultra Low Power Consumption

CMOS ASIC Design of a High Performance Digital Fuzzy Processor That Can Compute on Arbitrary Membership Functions

Energy Efficient Array Initialization Using Loop Unrolling with Partial Gray Code Sequence

Process Aware Ultra-High-Speed Hybrid Sensing Technique for Low Power Near-Threshold SRAM

A Dual Material Double-Layer Gate Stack Junctionless Transistor for Enhanced Analog Performance

Fault Aware Dynamic Adaptive Routing Using LBDR

On Designing Testable Reversible Circuits Using Gate Duplication

Communications in Computer and Information Science - VLSI Design and Test
Latest Publications