2016 IEEE 8th International Memory Workshop (IMW)
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52
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6
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Published By IEEE

9781467388337
Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

Demonstration of Yield Improvement for On-Via MTJ Using a 2-Mbit 1T-1MTJ STT-MRAM Test Chip

2016 ◽  
Author(s):  
Hiroki Koike ◽  
Sadahiko Miura ◽  
Hiroaki Honjo ◽  
Toshinari Watanabe ◽  
Hideo Sato ◽  
...  
Keyword(s):  
Test Chip ◽  
Yield Improvement

High Operating Temperature Reliability of Optimized Ge-Rich GST Wall PCM Devices

2016 ◽  
Author(s):  
J. Kluge ◽  
G. Navarro ◽  
V. Sousa ◽  
N. Castellani ◽  
S. Blonkowski ◽  
...  
Keyword(s):  
Operating Temperature ◽  
High Operating Temperature

A Bottom-Source Single-Gate Vertical Channel (BS-SGVC) 3D NAND Flash Architecture and Studies of Bottom Source Engineering

2016 ◽  
Author(s):  
Sheng-Chih Lai ◽  
Hang-Ting Lue ◽  
Tzu-Hsuan Hsu ◽  
Chen-Jun Wu ◽  
Li-Yang Liang ◽  
...  
Keyword(s):  
Vertical Channel ◽  
Nand Flash

An Efficient Sudden-Power-Off-Recovery Design with Guaranteed Booting Time for Solid State Drives

2016 ◽  
Author(s):  
Yu-Ming Chang ◽  
Ping-Hsien Lin ◽  
Ye-Jyun Lin ◽  
Tai-Chun Kuo ◽  
Yuan-Hao Chang ◽  
...  
Keyword(s):  
Solid State ◽  
Solid State Drives ◽  
Recovery Design

Hybrid CMOS-OxRAM Image Sensor for Overexposure Control

2016 ◽  
Author(s):  
Ashwani Kumar ◽  
Mukul Sarkar ◽  
Manan Suri
Keyword(s):  
Image Sensor ◽  
Hybrid Cmos

Demonstration of Reliable Triple-Level-Cell (TLC) Phase-Change Memory

2016 ◽  
Author(s):  
M. Stanisavljevic ◽  
H. Pozidis ◽  
A. Athmanathan ◽  
N. Papandreou ◽  
T. Mittelholzer ◽  
...  
Keyword(s):  
Phase Change ◽  
Phase Change Memory ◽  
Change Memory

Improvement of Poly-Si Channel Vertical Charge Trapping NAND Devices Characteristics by High Pressure D2/H2 Annealing.

2016 ◽  
Author(s):  
L. Breuil ◽  
J. G. Lisoni ◽  
R. Delhougne ◽  
C. L. Tan ◽  
J. Van Houdt ◽  
...  
Keyword(s):  
High Pressure ◽  
Charge Trapping
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