Comprehensive investigation on RF/analog parameters in ferroelectric tunnel FET

In this paper, the effect of ferroelectric layer thickness (tFE), coercive field (Ec), remnant polarization (Pr), and saturation polarization (Ps) on transfer characteristic is highlighted for a Ferroelectric Tunnel FET (Fe-TFET) through a commercial TCAD simulator. Further, we have reported the RF/analog parameters like transconductance (gm), output conductance (gd), gain (gm/gd), gate capacitance (Cgg), and cut off frequency (ft) for wide range of FE parameters in Fe-TFET. Improved RF/analog performance and transfer characteristic are obtained for low value of tFE, Pr, Ec, whereas, these behavior is degraded at high value of Ps.

Self-heating effect on logic performance of 6T-SRAM based on CFET device

CFET devices have become emerging and promising candidates for continuing Moore's law at sub-3 nm nodes owing to the area advantage of the N-P stacked structure, which markedly improves the integration of circuits. However, the introduction of vertical structure leads to severe thermal issues due to the self-heating effect, resulting in the degradation of the device and circuit performance. This paper mainly evaluates and analyzes the performance of the SRAM unit built using the CFET structure. The CFET-SRAM exhibits better performance than the conventional CMOS-SRAM in terms of access delay, even with the impact of self-heating. For the multi-fin-based CFET, although the total gate capacitance increases, the enhanced current improves the static noise margin significantly. However, as the number of channels expands, sheet-based CFET devices show more comprehensive superiority of area and performance.

Junctionless Gate-All-Around Nanowire FET with Asymmetric Spacer for Continued Scaling

In this paper we have performed scaling performance of asymmetric junctionless (JL) SOI nanowire FET at 10 nm gate length (LG). To study the device electrical performance various DC metrics like SS, DIBL, ION/IOFF ratio are performed. Even at 5 nm, the device has good electrical properties with subthreshold swing (SS) = 64 mV/dec, drain induced barrier lowering (DIBL) = 45 mV/V, and switching ratio (ION/IOFF) = 106 shows a higher level of electrostatic integrity. Moreover, to study scaling flexibility towards analog/RF applications various parameters like transconductance (I), transconductance generation factor (TGF), total gate capacitance (Cgg), and cutoff frequency (fT) are determined. Furthermore, the dynamic power (DP) and static power (SP) consumption of the device with scaling is also presented. The findings of the study show that asymmetric JL nanowire FET is one of the scaling possibilities.

Gate Capacitance and Off-State Characteristics of E-Mode p-GaN Gate AlGaN/GaN High-Electron-Mobility Transistors After Gate Stress Bias

This study investigated the gate capacitance and off-state characteristics of 650-V enhancement-mode p-GaN gate AlGaN/GaN high-electron-mobility transistors after various degrees of gate stress bias. A significant change was observed in the on-state capacitance when the gate stress bias was greater than 6 V. The corresponding threshold voltage exhibited a positive shift at low gate stress and a negative shift when the gate stress was greater than 6 V, which agreed with the shift observation from the I–V measurement. Moreover, the off-state leakage current increased significantly after the gate stress exceeded 6 V during the off-state characterization although the devices could be biased up to 1000 V without breakdown. The increase in the off-state leakage current would lead to higher power loss.

Analysis of junction capacitance characteristics of trench gate IGBT

Trench gate field termination IGBT represents the latest structure of insulated gate bipolar transistor (IGBT). Because the internal current of IGBT includes the charging and discharging current of gate capacitance and internal junction capacitance during switching transient, the influence of junction capacitance should be considered. The conductive channel of trench gate structure is different from that of planar gate structure, and the analysis method of junction capacitance using planar gate structure will inevitably bring some deviation. Based on the characteristics of trench gate structure, this paper analyzes the different expressions of internal gate-drain junction capacitance in two cases according to whether the base depletion layer can be widened to cover the trench gate, and finally carries out simulation and experimental verification.