2013 IEEE 43rd International Symposium on Multiple-Valued Logic
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Published By IEEE

9781467360678, 9780769549767

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

Synthesis of Balanced Ternary Reversible Logic Circuit

2013 IEEE 43rd International Symposium on Multiple-Valued Logic ◽

10.1109/ismvl.2013.53 ◽

2013 ◽

Cited By ~ 5

Author(s):

B. Mondal ◽

P. Sarkar ◽

P. K. Saha ◽

S. Chakraborty

Keyword(s):

Reversible Logic ◽

Logic Circuit

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Accurate and High-Speed Asynchronous Network-on-Chip Simulation Using Physical Wire-Delay Information

2013 IEEE 43rd International Symposium on Multiple-Valued Logic ◽

10.1109/ismvl.2013.11 ◽

2013 ◽

Cited By ~ 1

Author(s):

Takahiro Hanyu ◽

Yuma Watanabe ◽

Atsushi Matsumoto

Keyword(s):

High Speed ◽

Network On Chip ◽

Asynchronous Network ◽

Wire Delay ◽

On Chip ◽

Delay Information

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A Machine to Evaluate Decomposed Multi-Terminal Multi-Valued Decision Diagrams for Characteristic Functions

2013 IEEE 43rd International Symposium on Multiple-Valued Logic ◽

10.1109/ismvl.2013.6 ◽

2013 ◽

Author(s):

H. Nakahara ◽

T. Sasao ◽

M. Matsuura

Keyword(s):

Characteristic Functions ◽

Decision Diagrams

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Intersections with Slupecki Partial Clones on a Finite Set

2013 IEEE 43rd International Symposium on Multiple-Valued Logic ◽

10.1109/ismvl.2013.33 ◽

2013 ◽

Author(s):

L. Haddad ◽

K. Scholzel

Keyword(s):

Finite Set

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Highly Reliable Non-Volatile Logic Circuit Technology and Its Application

2013 IEEE 43rd International Symposium on Multiple-Valued Logic ◽

10.1109/ismvl.2013.32 ◽

2013 ◽

Cited By ~ 13

Author(s):

H. Kimura ◽

Z. Zhong ◽

Y. Mizuochi ◽

N. Kinouchi ◽

Y. Ichida ◽

...

Keyword(s):

Logic Circuit ◽

Circuit Technology

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Ternary Logic Network Justification Using Transfer Matrices

2013 IEEE 43rd International Symposium on Multiple-Valued Logic ◽

10.1109/ismvl.2013.57 ◽

2013 ◽

Cited By ~ 2

Author(s):

M. A. Thornton ◽

J. L. Dworak

Keyword(s):

Ternary Logic ◽

Transfer Matrices ◽

Logic Network

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Debugging of Reversible Circuits Using pDDs

2013 IEEE 43rd International Symposium on Multiple-Valued Logic ◽

10.1109/ismvl.2013.22 ◽

2013 ◽

Cited By ~ 2

Author(s):

L. Tague ◽

M. Soeken ◽

S. Minato ◽

R. Drechsler

Keyword(s):

Reversible Circuits

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Lowering Error Floors in Stochastic Decoding of LDPC Codes Based on Wire-Delay Dependent Asynchronous Updating

2013 IEEE 43rd International Symposium on Multiple-Valued Logic ◽

10.1109/ismvl.2013.35 ◽

2013 ◽

Cited By ~ 2

Author(s):

N. Onizawa ◽

W. J. Gross ◽

T. Hanyu ◽

V. C. Gaudet

Keyword(s):

Ldpc Codes ◽

Wire Delay ◽

Asynchronous Updating ◽

Stochastic Decoding ◽

Error Floors ◽

Delay Dependent

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[Publisher's information]

2013 IEEE 43rd International Symposium on Multiple-Valued Logic ◽

10.1109/ismvl.2013.62 ◽

2013 ◽

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Computational Medical and Health Care Technology

2013 IEEE 43rd International Symposium on Multiple-Valued Logic ◽

10.1109/ismvl.2013.20 ◽

2013 ◽

Cited By ~ 1

Author(s):

Y. Hata ◽

H. Nakajima

Keyword(s):

Health Care ◽

Health Care Technology ◽

Care Technology

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2013 IEEE 43rd International Symposium on Multiple-Valued LogicLatest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Synthesis of Balanced Ternary Reversible Logic Circuit

Accurate and High-Speed Asynchronous Network-on-Chip Simulation Using Physical Wire-Delay Information

A Machine to Evaluate Decomposed Multi-Terminal Multi-Valued Decision Diagrams for Characteristic Functions

Intersections with Slupecki Partial Clones on a Finite Set

Highly Reliable Non-Volatile Logic Circuit Technology and Its Application

Ternary Logic Network Justification Using Transfer Matrices

Debugging of Reversible Circuits Using pDDs

Lowering Error Floors in Stochastic Decoding of LDPC Codes Based on Wire-Delay Dependent Asynchronous Updating

[Publisher's information]

Computational Medical and Health Care Technology

2013 IEEE 43rd International Symposium on Multiple-Valued Logic
Latest Publications