Accurate and High-Speed Asynchronous Network-on-Chip Simulation Using Physical Wire-Delay Information

2013 ◽  
Author(s):  
Takahiro Hanyu ◽  
Yuma Watanabe ◽  
Atsushi Matsumoto
Keyword(s):  
High Speed ◽  
Network On Chip ◽  
Asynchronous Network ◽  
Wire Delay ◽  
On Chip ◽  
Delay Information

Investigation of transient fault effects in synchronous and asynchronous Network on Chip router

2011 ◽  
Vol 57 (1) ◽  
pp. 61-68 ◽  
Author(s):  
Pooria M. Yaghini ◽  
Ashkan Eghbal ◽  
Hossein Pedram ◽  
Hamid Reza Zarandi
Keyword(s):  
Network On Chip ◽  
Transient Fault ◽  
Asynchronous Network ◽  
On Chip

Power analysis for asynchronous network-on-chip

2013 ◽  
Vol 8 (S1) ◽  
pp. S72-S80
Author(s):  
Mohamed A. Abd El Ghany ◽  
Gursharan Reehal ◽  
Mohammed Ismail
Keyword(s):  
Power Analysis ◽  
Network On Chip ◽  
Asynchronous Network ◽  
On Chip

Network-on-Chip for Low Power MAP Decoder Using Folded Technique and CORDIC Algorithm for 5G Network

2021 ◽  
pp. 96-108
Author(s):  
Shiyamala S. ◽  
Vijay Soorya J. ◽  
Sanjay P. S. ◽  
Sathappan K.
Keyword(s):  
Turbo Codes ◽  
High Speed ◽  
Life Time ◽  
Full Adder ◽  
Network On Chip ◽  
Cordic Algorithm ◽  
Effective Manner ◽  
Constraint Length ◽  
On Chip ◽  
Map Decoder

With different constraint length (K), time scale, and code rate, modified MAP (maximum a posteriori) decoder architecture using folding technique, which has a linear life time chart, is developed, and dedicated turbo codes will be placed in a network-on-chip for various wireless applications. Folded techniques mitigated the number of latches used in interleaving and deinterleaving unit by adopting forward and backward resource utilizing method to M-2, where M is the number of rows and end-to-end delay get reduced to 2M. By replacing conventional full adder by high speed adder using 2 x 1 multiplexer to calculate the forward state metrics and reverse state metrics will minimize the power consumption utilization in an effective manner. In s similar way, CORDIC (Coordinated ROtation DIgital Computer) algorithm is used to calculate the LLR value and confer a highly precise value with less computational complexity by means of only shifting and adding methods.

Dual Monitoring Communication for Self-Aware Network-on-Chip

2012 ◽  
Vol 3 (3) ◽  
pp. 72-91
Author(s):  
Liang Guang ◽  
Ethiopia Nigussie ◽  
Juha Plosila ◽  
Hannu Tenhunen
Keyword(s):  
High Speed ◽  
Data Communication ◽  
Cmos Technology ◽  
Network On Chip ◽  
Time Profile ◽  
Self Awareness ◽  
Monitoring Networks ◽  
Communication Architecture ◽  
Run Time ◽  
On Chip

Self-aware and adaptive Network-on-Chip (NoC) with dual monitoring networks is presented. Proper monitoring interface is an essential prerequisite to adaptive system reconfiguration in parallel on-chip computing. This work proposes a DMC (dual monitoring communication) architecture to support self-awareness on the NoC platform. One type of monitoring communication is integrated with data channel, in order to trace the run-time profile of data communication in high-speed on-chip networking. The other type is separate from the data communication, and is needed to report the run-time profile to the supervising monitor. Direct latency monitoring on mesochronous NoC is presented as a case study and is directly traced in the integrated communication with a novel latency monitoring table in each router. The latency information is reported by the separate monitoring communication to the supervising monitor, which reconfigures the system to adjust the latency, for instance by dynamic voltage and frequency scaling. With quantitative evaluation using synthetic traces and real applications, the effectiveness and efficiency of direct latency monitoring with DMC architecture is demonstrated. The area overhead of DMC architecture is estimated to be small in 65nm CMOS technology.

scholarly journals Congestion-aware wireless network-on-chip for high-speed communication

Automatika ◽  
2019 ◽  
Vol 61 (1) ◽  
pp. 92-98
Author(s):  
M. Devanathan ◽  
V. Ranganathan ◽  
P. Sivakumar
Keyword(s):  
Wireless Network ◽  
High Speed ◽  
Network On Chip ◽  
On Chip ◽  
Congestion Aware

High Speed Low Power Ping Pong Buffering Based Network Interface for Network on Chip

2013 ◽  
Vol 9 (3) ◽  
pp. 322-331 ◽  
Author(s):  
K. Swaminathan ◽  
G. Lakshminarayanan ◽  
Seok-Bum Ko
Keyword(s):  
Low Power ◽  
High Speed ◽  
Network On Chip ◽  
Network Interface ◽  
Ping Pong ◽  
On Chip
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