[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design
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Using high-level primitives to speed up circuit partitioning in a mixed scan and non-scan environment for system level test generation

[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design ◽

10.1109/isvd.1991.185103 ◽

1991 ◽

Author(s):

S. Kode

Keyword(s):

Test Generation ◽

System Level ◽

Circuit Partitioning ◽

Speed Up ◽

High Level

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Method for testable design and for built-in test

[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design ◽

10.1109/isvd.1991.185136 ◽

1991 ◽

Author(s):

P.G. Petrov

Keyword(s):

Testable Design

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Overlap elimination in floorplans

[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design ◽

10.1109/isvd.1991.185110 ◽

1991 ◽

Cited By ~ 1

Author(s):

G. Vijayan

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Additive cellular automata (CA) as a primitive structure for signature analysis

[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design ◽

10.1109/isvd.1991.185123 ◽

1991 ◽

Cited By ~ 1

Author(s):

S. Misra ◽

P.P. Chaudhuri

Keyword(s):

Cellular Automata ◽

Signature Analysis ◽

Primitive Structure

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Design of high-speed VLSI circuits for mainframe computers

[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design ◽

10.1109/isvd.1991.185118 ◽

1991 ◽

Author(s):

S. Seinecke

Keyword(s):

High Speed ◽

Vlsi Circuits

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Automated data path synthesis to avoid global interconnects

[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design ◽

10.1109/isvd.1991.185085 ◽

1991 ◽

Cited By ~ 2

Author(s):

V.K. Raj ◽

C.S. Patwardhan

Keyword(s):

Data Path ◽

Global Interconnects ◽

Path Synthesis

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State machine design-an interactive approach

[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design ◽

10.1109/isvd.1991.185090 ◽

1991 ◽

Author(s):

J. Bastian ◽

A. Savargaonkar ◽

S. Venkateswaren ◽

K.R. Rao ◽

T.V.V.S. Nagesh ◽

...

Keyword(s):

State Machine ◽

Machine Design ◽

Interactive Approach

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An overlap model for routing

[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design ◽

10.1109/isvd.1991.185111 ◽

1991 ◽

Author(s):

K. Chaudhary ◽

P. Robinson

Keyword(s):

Overlap Model

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Linear ordering by stochastic evolution

[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design ◽

10.1109/isvd.1991.185105 ◽

1991 ◽

Cited By ~ 9

Author(s):

Y. Saab ◽

V. Rao

Keyword(s):

Linear Ordering ◽

Stochastic Evolution

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A practical approach to synchronous hardware verification

[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design ◽

10.1109/isvd.1991.185114 ◽

1991 ◽

Cited By ~ 1

Author(s):

G. Gopalakrishnan ◽

P. Jain

Keyword(s):

Hardware Verification ◽

Practical Approach

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[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI DesignLatest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Using high-level primitives to speed up circuit partitioning in a mixed scan and non-scan environment for system level test generation

Method for testable design and for built-in test

Overlap elimination in floorplans

Additive cellular automata (CA) as a primitive structure for signature analysis

Design of high-speed VLSI circuits for mainframe computers

Automated data path synthesis to avoid global interconnects

State machine design-an interactive approach

An overlap model for routing

Linear ordering by stochastic evolution

A practical approach to synchronous hardware verification

[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design
Latest Publications