Using high-level primitives to speed up circuit partitioning in a mixed scan and non-scan environment for system level test generation

Author(s):  
S. Kode
Author(s):  
Ramachandra P. Kunda ◽  
Jacob A. Abraham ◽  
Bharat Deep Rathi ◽  
Prakash Narain
Keyword(s):  
Speed Up ◽  

Aerospace ◽  
2021 ◽  
Vol 8 (3) ◽  
pp. 61
Author(s):  
Dominik Eisenhut ◽  
Nicolas Moebs ◽  
Evert Windels ◽  
Dominique Bergmann ◽  
Ingmar Geiß ◽  
...  

Recently, the new Green Deal policy initiative was presented by the European Union. The EU aims to achieve a sustainable future and be the first climate-neutral continent by 2050. It targets all of the continent’s industries, meaning aviation must contribute to these changes as well. By employing a systems engineering approach, this high-level task can be split into different levels to get from the vision to the relevant system or product itself. Part of this iterative process involves the aircraft requirements, which make the goals more achievable on the system level and allow validation of whether the designed systems fulfill these requirements. Within this work, the top-level aircraft requirements (TLARs) for a hybrid-electric regional aircraft for up to 50 passengers are presented. Apart from performance requirements, other requirements, like environmental ones, are also included. To check whether these requirements are fulfilled, different reference missions were defined which challenge various extremes within the requirements. Furthermore, figures of merit are established, providing a way of validating and comparing different aircraft designs. The modular structure of these aircraft designs ensures the possibility of evaluating different architectures and adapting these figures if necessary. Moreover, different criteria can be accounted for, or their calculation methods or weighting can be changed.


2021 ◽  
pp. 1-14
Author(s):  
Debo Dong ◽  
Dezhong Yao ◽  
Yulin Wang ◽  
Seok-Jun Hong ◽  
Sarah Genon ◽  
...  

Abstract Background Schizophrenia has been primarily conceptualized as a disorder of high-order cognitive functions with deficits in executive brain regions. Yet due to the increasing reports of early sensory processing deficit, recent models focus more on the developmental effects of impaired sensory process on high-order functions. The present study examined whether this pathological interaction relates to an overarching system-level imbalance, specifically a disruption in macroscale hierarchy affecting integration and segregation of unimodal and transmodal networks. Methods We applied a novel combination of connectome gradient and stepwise connectivity analysis to resting-state fMRI to characterize the sensorimotor-to-transmodal cortical hierarchy organization (96 patients v. 122 controls). Results We demonstrated compression of the cortical hierarchy organization in schizophrenia, with a prominent compression from the sensorimotor region and a less prominent compression from the frontal−parietal region, resulting in a diminished separation between sensory and fronto-parietal cognitive systems. Further analyses suggested reduced differentiation related to atypical functional connectome transition from unimodal to transmodal brain areas. Specifically, we found hypo-connectivity within unimodal regions and hyper-connectivity between unimodal regions and fronto-parietal and ventral attention regions along the classical sensation-to-cognition continuum (voxel-level corrected, p < 0.05). Conclusions The compression of cortical hierarchy organization represents a novel and integrative system-level substrate underlying the pathological interaction of early sensory and cognitive function in schizophrenia. This abnormal cortical hierarchy organization suggests cascading impairments from the disruption of the somatosensory−motor system and inefficient integration of bottom-up sensory information with attentional demands and executive control processes partially account for high-level cognitive deficits characteristic of schizophrenia.


Author(s):  
Daniel Tang ◽  
Mike Evans ◽  
Paul Briskham ◽  
Luca Susmel ◽  
Neil Sims

Self-pierce riveting (SPR) is a complex joining process where multiple layers of material are joined by creating a mechanical interlock via the simultaneous deformation of the inserted rivet and surrounding material. Due to the large number of variables which influence the resulting joint, finding the optimum process parameters has traditionally posed a challenge in the design of the process. Furthermore, there is a gap in knowledge regarding how changes made to the system may affect the produced joint. In this paper, a new system-level model of an inertia-based SPR system is proposed, consisting of a physics-based model of the riveting machine and an empirically-derived model of the joint. Model predictions are validated against extensive experimental data for multiple sets of input conditions, defined by the setting velocity, motor current limit and support frame type. The dynamics of the system and resulting head height of the joint are predicted to a high level of accuracy. Via a model-based case study, changes to the system are identified, which enable either the cycle time or energy consumption to be substantially reduced without compromising the overall quality of the produced joint. The predictive capabilities of the model may be leveraged to reduce the costs involved in the design and validation of SPR systems and processes.


2021 ◽  
Author(s):  
Lucas Bragança ◽  
Jeronimo Penha ◽  
Michael Canesche ◽  
Dener Ribeiro ◽  
José Augusto M. Nacif ◽  
...  

FPGAs are suitable to speed up gene regulatory network (GRN) algorithms with high throughput and energy efficiency. In addition, virtualizing FPGA using hardware generators and cloud resources increases the computing ability to achieve on-demand accelerations across multiple users. Recently, Amazon AWS provides high-performance Cloud's FPGAs. This work proposes an open source accelerator generator for Boolean gene regulatory networks. The generator automatically creates all hardware and software pieces from a high-level GRN description. We evaluate the accelerator performance and cost for CPU, GPU, and Cloud FPGA implementations by considering six GRN models proposed in the literature. As a result, the FPGA accelerator is at least 12x faster than the best GPU accelerator. Furthermore, the FPGA reaches the best performance per dollar in cloud services, at least 5x better than the best GPU accelerator.


2020 ◽  
Vol 3 (4) ◽  
pp. 1305
Author(s):  
Gerwyn Persulessy ◽  
Basuki Anondho

Development of high-level building construction projects that require complex equipment that can be used in high-level construction, equipment used to help complete construction projects called heavy equipment. One of the heavy equipment used in high-rise buildings is a tower crane. The use and layout of tower cranes can speed up the schedule and save on project costs. Therefore many methods have been developed to determine the tower crane layout. This study will discuss determining the location of tower cranes by discussing simulations. The location will be determined based on the site map data which is processed in the form of a geometric arrangement and tower crane data specifications. Location determination is done by comparing the total travel time of several simulated locations according to several different speed criteria in a construction project. Speed criteria are divided into four times the jib speed and trolley speed. Location of the location with the total travel time will be taken as the final result. Different speed criteria will make the total travel time change. ABSTRAKPerkembangan proyek pembangunan gedung bertingkat tinggi yang semakin kompleks menyebabkan diperlukannya peralatan yang dapat mempermudah pembangunan gedung bertingkat, peralatan yang digunakan untuk membantu menyelesaikan tugas konstruksi disebut alat berat. Salah satu peralatan berat yang digunakan pada gedung bertingkat tinggi adalah tower crane. Penggunaan dan tata letak tower crane yang baik dapat mempercepat jadwal dan menghemat biaya proyek. Oleh karena itu banyak dikembangkan metode-metode untuk menentukan tata letak tower crane. Penelitian ini akan membahas penetapan letak lokasi tower crane dengan pendekatan  simulasi. Letak lokasi akan ditetapkan berdasarkan data site map yang diolah dalam bentuk geometric layout dan data spesifikasi tower crane. Penetapan lokasi dilakukan dengan cara membandingkan total travel time dari beberapa lokasi yang disimulasi sesuai dengan beberapa kriteria kecepatan yang berbeda-beda pada suatu proyek konstruksi. Kriteria kecepatan terbagi menjadi empat berdasarkan besarnya kecepatan jib dan kecepatan trolley. Letak lokasi dengan total travel time terkecil akan diambil sebagai hasil akhir. Kriteria-kriteria kecepatan yang berbeda disimulasi akan membuat total travel time berubah.


2022 ◽  
Vol 6 (1) ◽  
Author(s):  
Marco Rossi ◽  
Sofia Vallecorsa

AbstractIn this work, we investigate different machine learning-based strategies for denoising raw simulation data from the ProtoDUNE experiment. The ProtoDUNE detector is hosted by CERN and it aims to test and calibrate the technologies for DUNE, a forthcoming experiment in neutrino physics. The reconstruction workchain consists of converting digital detector signals into physical high-level quantities. We address the first step in reconstruction, namely raw data denoising, leveraging deep learning algorithms. We design two architectures based on graph neural networks, aiming to enhance the receptive field of basic convolutional neural networks. We benchmark this approach against traditional algorithms implemented by the DUNE collaboration. We test the capabilities of graph neural network hardware accelerator setups to speed up training and inference processes.


VLSI Design ◽  
2012 ◽  
Vol 2012 ◽  
pp. 1-11
Author(s):  
M. Walton ◽  
O. Ahmed ◽  
G. Grewal ◽  
S. Areibi

Scatter Search is an effective and established population-based metaheuristic that has been used to solve a variety of hard optimization problems. However, the time required to find high-quality solutions can become prohibitive as problem sizes grow. In this paper, we present a hardware implementation of Scatter Search on a field-programmable gate array (FPGA). Our objective is to improve the run time of Scatter Search by exploiting the potentially massive performance benefits that are available through the native parallelism in hardware. When implementing Scatter Search we employ two different high-level languages (HLLs): Handel-C and Impulse-C. Our empirical results show that by effectively exploiting source-code optimizations, data parallelism, and pipelining, a 28x speed up over software can be achieved.


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