Design of high-speed VLSI circuits for mainframe computers

1991 ◽  
Author(s):  
S. Seinecke
Keyword(s):  
High Speed ◽  
Vlsi Circuits

Modeling the substrate effect in interconnect line characteristics of high-speed VLSI circuits

1998 ◽  
Vol 46 (10) ◽  
pp. 1436-1443 ◽  
Author(s):  
Jae-Kyung Wee ◽  
Young-June Park ◽  
Hong-Shick Min ◽  
Dae-Hyung Cho ◽  
Man-Ho Seung ◽  
...  
Keyword(s):  
High Speed ◽  
Vlsi Circuits ◽  
Substrate Effect

scholarly journals Implementation of time efficient hybrid multiplier for FFT computation

2018 ◽  
Vol 7 (2.7) ◽  
pp. 409 ◽  
Author(s):  
R Nikhil ◽  
G V. S. Veerendra ◽  
J Rahul M. S. Sri Harsha ◽  
Dr V. S. V. Prabhakar
Keyword(s):  
Power Efficiency ◽  
High Speed ◽  
Vlsi Circuits ◽  
Low Power Consumption ◽  
Chip Area ◽  
Booth Multiplier ◽  
Low Delay ◽  
Wallace Tree ◽  
Wallace Tree Multiplier ◽  
Carry Save Adders

Now a days in designing a VLSI circuits we are coming across many problems such as high power intake, delay and large utilization of chip area in order to overcome these problems a new architectures are developed. In our project we deals with FFT computation which internally involves series of multiplication and addition therefore requirement of efficient multipliers is needed and therefore we come across two high speed improved multipliers Booth multiplier and Wallace tree multiplier which are good in terms of power efficiency and low output delay. The main aim of our project involves hybridizing the both Wallace multiplier and Booth multiplier which yields low delay and low power consumption than compared to individual multipliers. The Booth multiplier is used for reduction of partial products and for addition operations carry save adders is used in Wallace tree multipliers and thus hybrid is designed by combining both the algorithms which in turn produces better results and they can be observed in comparisons tabular column in our documentation. These multipliers can be designed in many ways such using cmos layout techniques and also using Verilog programming and we have chosen Verilog programming which requires Xilinx software and codes are developed in gate level design model for the respective multiplier models and the results will be tabulated.  

PERTURBATION TECHNIQUES FOR ON-CHIP LEARNING WITH ANALOGUE VLSI MLPs

1996 ◽  
Vol 06 (02) ◽  
pp. 93-113 ◽  
Author(s):  
GRAHAM CAIRNS ◽  
LIONEL TARASSENKO
Keyword(s):  
High Speed ◽  
Vlsi Circuits ◽  
Benchmark Problems ◽  
Perturbation Techniques ◽  
Successful Operation ◽  
Reliable Performance ◽  
Analogue Vlsi ◽  
Computationally Intensive ◽  
On Chip ◽  
Simple Integration

Microelectronic neural network technology has become sufficiently mature over the past few years that reliable performance can now be obtained from VLSI circuits under carefully controlled conditions (see Refs. 8 or 13 for example). The use of analogue VLSI allows low power, area efficient hardware realisations which can perform the computationally intensive feed-forward operation of neural networks at high speed, making real-time applications possible. In this paper we focus on important issues for the successful operation and implementation of on-chip learning with such analogue VLSI neural hardware, in particular the issue of weight precision. We first review several perturbation techniques which have been proposed to train multi-layer perceptron (MLP) networks. We then present a novel error criterion which performs well on benchmark problems and which allows simple integration of error measurement hardware for complete on-chip learning systems.

scholarly journals Incremental Automatic Correction for Digital VLSI Circuits

2020 ◽  
Author(s):  
Lamya Gaber ◽  
Aziza I. Hussein ◽  
Mohammed Moness
Keyword(s):  
Computer Aided Design ◽  
High Speed ◽  
Negative Impact ◽  
Positive Impact ◽  
Vlsi Circuits ◽  
Digital Vlsi ◽  
Large Numbers ◽  
Aided Design ◽  
The Impact ◽  
Compact Test

The impact of the recent exponential increase in complexity of digital VLSI circuits has heavily affected verification methodologies. Many advances toward verification and debugging techniques of digital VLSI circuits have relied on Computer Aided Design (CAD). Existing techniques are highly dependent on specialized test patterns with specific numbers increased by the rising complexity of VLSI circuits. A second problem arises in the form of large sizes of injecting circuits for correction and large number of SAT solver calls with a negative impact on the resultant running time. Three goals arise: first, diminishing dependence on a given test pattern by incrementally generating compact test patterns corresponding to design errors during the rectification process. Second, to reduce the size of in-circuit mutation circuit for error-fixing process. Finally, distribution of test patterns can be performed in parallel with a positive impact on digital VLSI circuits with large numbers of inputs and outputs. The experimental results illustrate that the proposed incremental correction algorithm can fix design bugs of type gate replacements in several digital VLSI circuits from ISCAS'85 with high speed and full accuracy. The speed of proposed Auto-correction mechanism outperforms the latest existing methods around 4.8x using ISCAS'85 benchmarks. The parallel distribution of test patterns on digital VLSI circuits during generating new compact test patterns achieves speed around 1.2x compared to latest methods.

scholarly journals POWER REDUCTION TECHNIQUES IN VLSI

2020 ◽  
Vol 5 (2) ◽  
pp. 123-129
Author(s):  
Mehar Sharma ◽  
Neeraj Gupta ◽  
Rashmi Gupta
Keyword(s):  
Power Dissipation ◽  
High Speed ◽  
Power Reduction ◽  
Vlsi Circuits ◽  
Abstraction Level ◽  
Reduction Techniques ◽  
Increasing Trend ◽  
Different Types ◽  
The Given

The paper investigates different level of techniques used for power reduction in VLSI. Before,most of the researches were oriented towards bringing about high speed and miniaturization.At present, because of the increasing trend of compact devices, the requirement for low powerconsuming circuits have also increased. This necessitates the need to align the research forreducing power dissipation in VLSI circuits. In the given paper we will briefly discuss aboutthe different types of power reduction techniques at design abstraction level which are adoptedin industries now-a-days. The comparison of traditional techniques and present techniquesare also covered in this paper.

scholarly journals Low Power VLSI Design Techniques: A Review

2021 ◽  
Vol 23 (11) ◽  
pp. 172-183
Author(s):  
Ketan J. Raut ◽  
◽  
Abhijit V. Chitre ◽  
Minal S. Deshmukh ◽  
Kiran Magar ◽  
...  
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
High Speed ◽  
Vlsi Design ◽  
Cmos Technology ◽  
Vlsi Circuits ◽  
Optimization Techniques ◽  
Battery Life ◽  
Dynamic Power ◽  
Cmos Vlsi

Since CMOS technology consumes less power it is a key technology for VLSI circuit design. With technologies reaching the scale of 10 nm, static and dynamic power dissipation in CMOS VLSI circuits are major issues. Dynamic power dissipation is increased due to requirement of high speed and static power dissipation is at much higher side now a days even compared to dynamic power dissipation due to very high gate leakage current and subthreshold leakage. Low power consumption is equally important as speed in many applications since it leads to a reduction in the package cost and extended battery life. This paper surveys contemporary optimization techniques that aims low power dissipation in VLSI circuits.

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