Radiation-Tolerant All-Digital PLL/CDR with Varactorless LC DCO in 65 nm CMOS

This paper presents the first fully integrated radiation-tolerant All-Digital Phase-Locked Loop (PLL) and Clock and Data Recovery (CDR) circuit for wireline communication applications. Several radiation hardening techniques are proposed to achieve state-of-the-art immunity to Single-Event Effects (SEEs) up to 62.52/mg as well as tolerance to the Total Ionizing Dose (TID) exceeding 1.5Grad. The LC Digitally Controlled Oscillator (DCO) is implemented without MOS varactors, avoiding the use of a highly SEE sensitive circuit element. The circuit is designed to operate at reference clock frequencies from 40–320 or at data rates from 40Mbps–320Mbps and displays a jitter performance of 520 with a power dissipation of only 11 and an FOM of −235 .

Hybrid Cross Coupled Differential Pair and Colpitts Quadrature Digitally Controlled Oscillator Architecture

Growing importance of wireless communication systems forces reduction of power consumption of the designed integrated circuits. The paper focuses on minimization of power consumption in a digitally controlled oscillator (DCO) that can be employed as oscillator in GPS/Galileo receiver. The new hybrid architecture of DCO combines good phase noise performance of a Colpitts oscillator and relaxed startup conditions of a cross-coupled differential pair oscillator. The proposed new DCO generates a quadrature signal in a current reused frequency divider. Such solution allows of the dissipated power to be reduced. The DCO has been implemented in 110 nm CMOS technology. It generates output signal in frequency range from 1.52 GHz to 1.6 GHz and consumes 1.1 mW from 1.5 V supply voltage. The measured phase noise equals −116 dBc/Hz at 1 MHz offset from 1.575 GHz output signal.

Digitally Controlled Oscillator with High Timing Resolution and Low Complexity for Clock Generation

This paper presents a digitally controlled oscillator (DCO) with a low-complexity circuit structure that combines multiple delay circuits to achieve a high timing resolution and wide output frequency range simultaneously while also significantly reducing the overall power consumption. A 0.18 µm complementary metal–oxide–semiconductor standard process was used for the design, and measurements showed that the chip had a minimum controllable timing resolution of 4.81 ps and power consumption of 142 µW with an output signal of 364 MHz. When compared with other designs using advanced processes, the proposed DCO demonstrated the best power-to-frequency ratio. Therefore, it can output a signal at the required frequency more efficiently in terms of power consumption. Additionally, because the proposed DCO uses digital logic gates only, a cell-based design flow can be implemented. Hence, the proposed DCO is not only easy to implement in different processes but also easy to integrate with other digital circuits.

Optimum Layout of Low Power LC-Based Digitally Controlled Oscillator for Bluetooth Low Energy in a 4G/5G LTE System

This paper presents an optimum layout method of a low-power, digitally controlled oscillator (DCO) for a Bluetooth low-energy (BLE) transceiver in a 4G/5G LTE system. For the optimal LC-based DCO layout, three different layouts, including different gm cell locations and an Al metal layer, were implemented, and performance was compared and verified for BLE application. The implemented neck DCO (NDCO), where the gm cell is located in the neck of the main inductor, showed superior performance compared to other layouts in terms of low phase noise and low power consumption. The designed NDCO had a low phase noise of −116.1 dBc/Hz at 1 MHz with a 0.5 mW power consumption. The supply voltage and oscillation frequency range were 0.8 V and 4.7–5.7 GHz, respectively, and the NDCO designed with the optimal layout had a good figure-of-merit of −192.6 dBc/Hz.