2017 IEEE International Symposium on Nanoelectronic and Information Systems (iNIS)
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9781538613566

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Current Profile Generated by Gating Logic Reduces Power Supply Noise of Integrated CPU Chip

2017 IEEE International Symposium on Nanoelectronic and Information Systems (iNIS) ◽

10.1109/inis.2017.53 ◽

2017 ◽

Cited By ~ 2

Author(s):

Alak Majumder ◽

Pritam Bhattacharjee

Keyword(s):

Power Supply ◽

Power Supply Noise ◽

Current Profile ◽

Supply Noise

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2017 IEEE International Symposium on Nanoelectronic and Information Systems (iNIS) ◽

10.1109/inis.2017.4 ◽

2017 ◽

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Implementation of a 6 GHz MEMS Switch

2017 IEEE International Symposium on Nanoelectronic and Information Systems (iNIS) ◽

10.1109/inis.2017.25 ◽

2017 ◽

Author(s):

Saurabh Chaturvedi ◽

Mladen Bozanic ◽

Saurabh Sinha

Keyword(s):

Mems Switch

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A Novel Intrusion Detection Algorithm: An AODV Routing Protocol Case Study

2017 IEEE International Symposium on Nanoelectronic and Information Systems (iNIS) ◽

10.1109/inis.2017.32 ◽

2017 ◽

Cited By ~ 3

Author(s):

Gurveen Vaseer ◽

Garima Ghai ◽

Pushpinder Singh Patheja

Keyword(s):

Intrusion Detection ◽

Routing Protocol ◽

Detection Algorithm ◽

Aodv Routing Protocol

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Design and Simulation of SF-FinFET and SD-FinFET and Their Performance in Analog, RF and Digital Applications

2017 IEEE International Symposium on Nanoelectronic and Information Systems (iNIS) ◽

10.1109/inis.2017.49 ◽

2017 ◽

Cited By ~ 2

Author(s):

Syed Samsuz Zaman ◽

Pankaj Kumar ◽

Manash Pratim Sarma ◽

Ashok Ray ◽

Gaurav Trivedi

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A Firefly Algorithm Driven Approach for High Level Synthesis

2017 IEEE International Symposium on Nanoelectronic and Information Systems (iNIS) ◽

10.1109/inis.2017.13 ◽

2017 ◽

Author(s):

Pallabi Sarkar ◽

Anirban Sengupta ◽

Santosh Rathlavat ◽

Mrinal Kanti Naskar

Keyword(s):

Firefly Algorithm ◽

High Level Synthesis ◽

High Level

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Gate Metal Work Function Engineering for the Improvement of Electrostatic Behaviour of Doped Tunnel Field Effect Transistor

2017 IEEE International Symposium on Nanoelectronic and Information Systems (iNIS) ◽

10.1109/inis.2017.47 ◽

2017 ◽

Cited By ~ 2

Author(s):

Deepak Soni ◽

Dheeraj Sharma ◽

Shivendra Yadav ◽

Mohd. Aslam ◽

Dharmendra Singh Yadav ◽

...

Keyword(s):

Work Function ◽

Field Effect ◽

Field Effect Transistor ◽

Metal Work Function ◽

Effect Transistor ◽

Tunnel Field Effect Transistor ◽

Metal Work

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Routing Algorithm for Application-Specific Network-on-Chip with Irregular Core Sizes

2017 IEEE International Symposium on Nanoelectronic and Information Systems (iNIS) ◽

10.1109/inis.2017.21 ◽

2017 ◽

Author(s):

Grandhi Sai Anirudh ◽

J. Soumya

Keyword(s):

Routing Algorithm ◽

Network On Chip ◽

On Chip ◽

Application Specific

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MSM: Performance Enhancing Area and Congestion Aware Network-on-Chip Architecture

2017 IEEE International Symposium on Nanoelectronic and Information Systems (iNIS) ◽

10.1109/inis.2017.61 ◽

2017 ◽

Author(s):

Tuhin Subhra Das ◽

Prasun Ghosal

Keyword(s):

Network On Chip ◽

On Chip ◽

Congestion Aware ◽

Performance Enhancing

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Keynotes [3 abstracts]

2017 IEEE International Symposium on Nanoelectronic and Information Systems (iNIS) ◽

10.1109/inis.2017.64 ◽

2017 ◽

Download Full-text

2017 IEEE International Symposium on Nanoelectronic and Information Systems (iNIS)
Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Current Profile Generated by Gating Logic Reduces Power Supply Noise of Integrated CPU Chip

Table of contents

Implementation of a 6 GHz MEMS Switch

A Novel Intrusion Detection Algorithm: An AODV Routing Protocol Case Study

Design and Simulation of SF-FinFET and SD-FinFET and Their Performance in Analog, RF and Digital Applications

A Firefly Algorithm Driven Approach for High Level Synthesis

Gate Metal Work Function Engineering for the Improvement of Electrostatic Behaviour of Doped Tunnel Field Effect Transistor

Routing Algorithm for Application-Specific Network-on-Chip with Irregular Core Sizes

MSM: Performance Enhancing Area and Congestion Aware Network-on-Chip Architecture

Keynotes [3 abstracts]

Export Citation Format

2017 IEEE International Symposium on Nanoelectronic and Information Systems (iNIS)Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Current Profile Generated by Gating Logic Reduces Power Supply Noise of Integrated CPU Chip

Table of contents

Implementation of a 6 GHz MEMS Switch

A Novel Intrusion Detection Algorithm: An AODV Routing Protocol Case Study

Design and Simulation of SF-FinFET and SD-FinFET and Their Performance in Analog, RF and Digital Applications

A Firefly Algorithm Driven Approach for High Level Synthesis

Gate Metal Work Function Engineering for the Improvement of Electrostatic Behaviour of Doped Tunnel Field Effect Transistor

Routing Algorithm for Application-Specific Network-on-Chip with Irregular Core Sizes

MSM: Performance Enhancing Area and Congestion Aware Network-on-Chip Architecture

Keynotes [3 abstracts]

2017 IEEE International Symposium on Nanoelectronic and Information Systems (iNIS)
Latest Publications