Current Profile Generated by Gating Logic Reduces Power Supply Noise of Integrated CPU Chip

2017 IEEE International Symposium on Nanoelectronic and Information Systems (iNIS) ◽

10.1109/inis.2017.53 ◽

2017 ◽

Author(s):

Alak Majumder ◽

Pritam Bhattacharjee

Keyword(s):

Power Supply ◽

Power Supply Noise ◽

Current Profile ◽

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AC Power Supply Noise Simulation of CMOS Microprocessor with LSI Chip-Package-Board Integrated Model

IEICE Transactions on Electronics ◽

10.1587/transele.e97.c.264 ◽

2014 ◽

Vol E97.C (4) ◽

pp. 264-271 ◽

Author(s):

Kumpei YOSHIKAWA ◽

Kouji ICHIKAWA ◽

Makoto NAGATA

Keyword(s):

Power Supply ◽

Integrated Model ◽

Power Supply Noise ◽

Supply Noise ◽

Noise Simulation ◽

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Power-Supply-Noise-Aware Timing Analysis and Test Pattern Regeneration

IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences ◽

10.1587/transfun.e99.a.2320 ◽

2016 ◽

Vol E99.A (12) ◽

pp. 2320-2327

Author(s):

Cheng-Yu HAN ◽

Yu-Ching LI ◽

Hao-Tien KAN ◽

James Chien-Mo LI

Keyword(s):

Power Supply ◽

Test Pattern ◽

Timing Analysis ◽

Power Supply Noise ◽

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Power Supply Noise-Aware Scan Test Pattern Reshaping for At-Speed Delay Fault Testing of Monolithic 3D ICs *

2020 IEEE 29th Asian Test Symposium (ATS) ◽

10.1109/ats49688.2020.9301568 ◽

2020 ◽

Author(s):

Shao-Chun Hung ◽

Yi-Chen Lu ◽

Sung Kyu Lim ◽

Krishnendu Chakrabarty

Keyword(s):

Power Supply ◽

Test Pattern ◽

Power Supply Noise ◽

Fault Testing ◽

Delay Fault ◽

Delay Fault Testing ◽

3D Ics ◽

Scan Test ◽

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A GALS Design with Opposite-Phase Local Clock Assignment for Power Supply Noise Reduction

2018 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) ◽

10.1109/apccas.2018.8605670 ◽

2018 ◽

Author(s):

Nguyen Van Toan ◽

Dam Minh Tung ◽

Jeong-Gun Lee

Keyword(s):

Noise Reduction ◽

Power Supply ◽

Power Supply Noise ◽

Local Clock ◽

Opposite Phase ◽

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Single-chip multi-processor integrating quadruple 8-way vliw processors with interface timing analysis considering power supply noise

Asia and South Pacific Conference on Design Automation, 2006. ◽

10.1109/aspdac.2006.1594741 ◽

2006 ◽

Author(s):

S. Imai ◽

A. Inoue ◽

M. Matsumura ◽

K. Kawasaki ◽

A. Suga

Keyword(s):

Power Supply ◽

Timing Analysis ◽

Power Supply Noise ◽

Single Chip ◽

Vliw Processors ◽

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Power supply noise in accurate delay model for the sub-threshold domain

Integration ◽

10.1016/j.vlsi.2015.02.001 ◽

2015 ◽

Vol 50 ◽

pp. 127-136

Author(s):

Pasquale Corsonello ◽

Fabio Frustaci ◽

Stefania Perri

Keyword(s):

Power Supply ◽

Delay Model ◽

Power Supply Noise ◽

Supply Noise ◽

Accurate Delay Model

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Floorplanning with power supply noise avoidance

Proceedings of the ASP-DAC Asia and South Pacific Design Automation Conference, 2003. ◽

10.1109/aspdac.2003.1195053 ◽

2003 ◽

Author(s):

Hung-Ming Chen ◽

Li-Da Huang ◽

I-Min Liu ◽

Minghorng Lai ◽

D.F. Wong

Keyword(s):

Power Supply ◽

Power Supply Noise ◽

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Layout-Aware Critical Path Delay Test Under Maximum Power Supply Noise Effects

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/tcad.2011.2163159 ◽

2011 ◽

Vol 30 (12) ◽

pp. 1923-1934 ◽

Author(s):

Junxia Ma ◽

Mohammad Tehranipoor

Keyword(s):

Power Supply ◽

Critical Path ◽

Maximum Power ◽

Power Supply Noise ◽

Noise Effects ◽

Critical Path Delay ◽

Supply Noise ◽

Path Delay Test

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Delay testing considering power supply noise effects

International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034) ◽

10.1109/test.1999.805629 ◽

2003 ◽

Author(s):

A. Krstic ◽

Yi-Min Jiang ◽

Kwang-Ting Cheng

Keyword(s):

Power Supply ◽

Delay Testing ◽

Power Supply Noise ◽

Noise Effects ◽

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A vector-based approach for power supply noise analysis in test compaction

IEEE International Conference on Test, 2005. ◽

10.1109/test.2005.1584012 ◽

2006 ◽

Author(s):

Jing Wang ◽

Ziding Yue ◽

Xiang Lu ◽

Wangqi Qiu ◽

Weiping Shi ◽

...

Keyword(s):

Power Supply ◽

Noise Analysis ◽

Power Supply Noise ◽

Test Compaction ◽

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