2001 Southwest Symposium on Mixed-Signal Design (Cat. No.01EX475)
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Noise in phase-locked loops

2001 Southwest Symposium on Mixed-Signal Design (Cat. No.01EX475) ◽

10.1109/ssmsd.2001.914927 ◽

2002 ◽

Cited By ~ 51

Author(s):

A. Hajimiri

Keyword(s):

Phase Locked Loops

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Watermarking of standard-cell feedthroughs in mixed-signal design

2001 Southwest Symposium on Mixed-Signal Design (Cat. No.01EX475) ◽

10.1109/ssmsd.2001.914950 ◽

2002 ◽

Cited By ~ 2

Author(s):

D.L. Irby ◽

R.D. Newbould ◽

J.D. Carothers ◽

J.J. Rodriguez ◽

W.T. Holman

Keyword(s):

Signal Design ◽

Standard Cell ◽

Mixed Signal

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A simple method for relating time- and frequency-domain measures of oscillator performance

2001 Southwest Symposium on Mixed-Signal Design (Cat. No.01EX475) ◽

10.1109/ssmsd.2001.914928 ◽

2002 ◽

Cited By ~ 9

Author(s):

J.A. McNeill

Keyword(s):

Frequency Domain ◽

Simple Method

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Automated power supply noise reduction via optimized distributed capacitors insertion

2001 Southwest Symposium on Mixed-Signal Design (Cat. No.01EX475) ◽

10.1109/ssmsd.2001.914959 ◽

2002 ◽

Cited By ~ 4

Author(s):

M. Graziano ◽

G. Masera ◽

G. Piccinini ◽

M. Zamboni

Keyword(s):

Noise Reduction ◽

Power Supply ◽

Power Supply Noise ◽

Supply Noise

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A front-end filter with automatic center frequency tuning circuitry

2001 Southwest Symposium on Mixed-Signal Design (Cat. No.01EX475) ◽

10.1109/ssmsd.2001.914932 ◽

2002 ◽

Cited By ~ 1

Author(s):

Y. Chang ◽

J. Wills ◽

J. Choma

Keyword(s):

Frequency Tuning ◽

Center Frequency ◽

Front End

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General SSCR vs. cycle-to-cycle jitter relationship with application to the phase noise in PLL

2001 Southwest Symposium on Mixed-Signal Design (Cat. No.01EX475) ◽

10.1109/ssmsd.2001.914933 ◽

2002 ◽

Cited By ~ 20

Author(s):

A. Zanchi ◽

A. Bonfanti ◽

S. Levantino ◽

C. Samori

Keyword(s):

Phase Noise

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Gate recognition and netlist reduction for switch-level simulation of dynamic bit-level systolic arrays

2001 Southwest Symposium on Mixed-Signal Design (Cat. No.01EX475) ◽

10.1109/ssmsd.2001.914937 ◽

2002 ◽

Author(s):

A. Blotti ◽

F. Mannozzi ◽

R. Roncella ◽

R. Saletti ◽

F. Tinfena

Keyword(s):

Systolic Arrays

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Low voltage continuous time tunable high frequency filters based on floating gates and dynamic biasing techniques

2001 Southwest Symposium on Mixed-Signal Design (Cat. No.01EX475) ◽

10.1109/ssmsd.2001.914946 ◽

2002 ◽

Author(s):

F. Munoz ◽

R.G. Carvajal ◽

A. Torralba ◽

J. Tombs ◽

J. Ramirez-Angulo

Keyword(s):

Continuous Time ◽

High Frequency ◽

Low Voltage ◽

Floating Gates ◽

Dynamic Biasing

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Behavioral model of pipeline ADC by using SIMULINK(R)

2001 Southwest Symposium on Mixed-Signal Design (Cat. No.01EX475) ◽

10.1109/ssmsd.2001.914955 ◽

2002 ◽

Cited By ~ 11

Author(s):

E. Bilhan ◽

P.C. Estrada-Gutierrez ◽

A.Y. Valero-Lopez ◽

F. Maloberti

Keyword(s):

Behavioral Model ◽

Pipeline Adc

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Design of multistage feedforward compensated opamps

2001 Southwest Symposium on Mixed-Signal Design (Cat. No.01EX475) ◽

10.1109/ssmsd.2001.914930 ◽

2002 ◽

Author(s):

A. Thomsen

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2001 Southwest Symposium on Mixed-Signal Design (Cat. No.01EX475)Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Noise in phase-locked loops

Watermarking of standard-cell feedthroughs in mixed-signal design

A simple method for relating time- and frequency-domain measures of oscillator performance

Automated power supply noise reduction via optimized distributed capacitors insertion

A front-end filter with automatic center frequency tuning circuitry

General SSCR vs. cycle-to-cycle jitter relationship with application to the phase noise in PLL

Gate recognition and netlist reduction for switch-level simulation of dynamic bit-level systolic arrays

Low voltage continuous time tunable high frequency filters based on floating gates and dynamic biasing techniques

Behavioral model of pipeline ADC by using SIMULINK(R)

Design of multistage feedforward compensated opamps

2001 Southwest Symposium on Mixed-Signal Design (Cat. No.01EX475)
Latest Publications