1998 IEEE Workshop on Signal Processing Systems. SIPS 98. Design and Implementation (Cat. No.98TH8374)
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Loop Scheduling Algorithm For Timing And Memory Operation Minimization With Register Constraint

1998 IEEE Workshop on Signal Processing Systems. SIPS 98. Design and Implementation (Cat. No.98TH8374) ◽

10.1109/sips.1998.715821 ◽

2005 ◽

Author(s):

F. Chen ◽

S. Tongsima ◽

E.H.-M. Sha

Keyword(s):

Scheduling Algorithm ◽

Loop Scheduling ◽

Operation Minimization

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Array signal processing for a wireless MEM sensor network

1998 IEEE Workshop on Signal Processing Systems. SIPS 98. Design and Implementation (Cat. No.98TH8374) ◽

10.1109/sips.1998.715764 ◽

2002 ◽

Author(s):

K. Yao ◽

R.E. Hudson ◽

C.W. Reed ◽

D. Chen ◽

T.L. Tung ◽

...

Keyword(s):

Signal Processing ◽

Sensor Network ◽

Array Signal Processing

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Low-power GPS receiver design

1998 IEEE Workshop on Signal Processing Systems. SIPS 98. Design and Implementation (Cat. No.98TH8374) ◽

10.1109/sips.1998.715763 ◽

2002 ◽

Author(s):

T.H. Meng

Keyword(s):

Low Power ◽

Receiver Design ◽

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A portable system for high-resolution digital image acquisition using wavelet image compression

1998 IEEE Workshop on Signal Processing Systems. SIPS 98. Design and Implementation (Cat. No.98TH8374) ◽

10.1109/sips.1998.715776 ◽

2002 ◽

Author(s):

U. Schelinski ◽

S. Danz ◽

K. Frommhagen ◽

M. Scholles ◽

M. Schwarzenberg

Keyword(s):

High Resolution ◽

Image Compression ◽

Digital Image ◽

Image Acquisition ◽

Portable System ◽

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A flexible approach and VLSI architecture for computing discrete time-frequency distribution

1998 IEEE Workshop on Signal Processing Systems. SIPS 98. Design and Implementation (Cat. No.98TH8374) ◽

10.1109/sips.1998.715781 ◽

2002 ◽

Author(s):

T. Le ◽

T. Dombek ◽

J. Becker ◽

M. Glesner

Keyword(s):

Frequency Distribution ◽

Discrete Time ◽

Vlsi Architecture ◽

Flexible Approach ◽

Time Frequency ◽

Time Frequency Distribution

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Design and implementation of a nonlinear acoustic echo canceller

1998 IEEE Workshop on Signal Processing Systems. SIPS 98. Design and Implementation (Cat. No.98TH8374) ◽

10.1109/sips.1998.715802 ◽

2002 ◽

Author(s):

A. Ben Rabaa ◽

A. Mtibaa ◽

M. Abid ◽

R. Tourki

Keyword(s):

Echo Canceller ◽

Design And Implementation ◽

Acoustic Echo ◽

Nonlinear Acoustic

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Digit-serial reconfigurable FPGA logic block architecture

1998 IEEE Workshop on Signal Processing Systems. SIPS 98. Design and Implementation (Cat. No.98TH8374) ◽

10.1109/sips.1998.715809 ◽

2002 ◽

Author(s):

H. Lee ◽

G.E. Sobelman

Keyword(s):

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A core generator for fully synthesizable and highly parameterizable RISC-cores for system-on-chip designs

1998 IEEE Workshop on Signal Processing Systems. SIPS 98. Design and Implementation (Cat. No.98TH8374) ◽

10.1109/sips.1998.715818 ◽

2002 ◽

Author(s):

M. Berekovic ◽

D. Heistermann ◽

P. Pirsch

Keyword(s):

System On Chip ◽

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Re-evaluating MPEG motion compensation search criteria

1998 IEEE Workshop on Signal Processing Systems. SIPS 98. Design and Implementation (Cat. No.98TH8374) ◽

10.1109/sips.1998.715775 ◽

2002 ◽

Author(s):

B. Bishop ◽

T.P. Kelliher ◽

R.M. Owens ◽

M.J. Irwin

Keyword(s):

Motion Compensation

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A uniform analysis method for DSP architectures and instruction sets with a comprehensive example

1998 IEEE Workshop on Signal Processing Systems. SIPS 98. Design and Implementation (Cat. No.98TH8374) ◽

10.1109/sips.1998.715815 ◽

2002 ◽

Author(s):

R.E. Owen ◽

D. Martin

Keyword(s):

Analysis Method ◽

Instruction Sets

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