2012 Symposium on VLSI Circuits (VLSIC)
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TOTAL DOCUMENTS

103

(FIVE YEARS 0)

H-INDEX

14

(FIVE YEARS 0)

Published By IEEE

9781467308496, 9781467308489, 9781467308458

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

A 7b, 3.75ps resolution two-step time-to-digital converter in 65nm CMOS using pulse-train time amplifier

2012 Symposium on VLSI Circuits (VLSIC) ◽

10.1109/vlsic.2012.6243855 ◽

2012 ◽

Author(s):

KwangSeok Kim ◽

YoungHwa Kim ◽

WonSik Yu ◽

SeongHwan Cho

Keyword(s):

Pulse Train ◽

Digital Converter ◽

Time To Digital Converter ◽

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A 635pW battery voltage supervisory circuit for miniature sensor nodes

2012 Symposium on VLSI Circuits (VLSIC) ◽

10.1109/vlsic.2012.6243860 ◽

2012 ◽

Author(s):

Inhee Lee ◽

Suyoung Bang ◽

Yoonmyung Lee ◽

Yejoong Kim ◽

Gyouho Kim ◽

...

Keyword(s):

Sensor Nodes ◽

Battery Voltage ◽

Miniature Sensor

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An on-die all-digital delay measurement circuit with 250fs accuracy

2012 Symposium on VLSI Circuits (VLSIC) ◽

10.1109/vlsic.2012.6243808 ◽

2012 ◽

Author(s):

Mozhgan Mansuri ◽

Bryan Casper ◽

Frank O'Mahony

Keyword(s):

Measurement Circuit ◽

Delay Measurement

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Adaptive multi-pulse program scheme based on tunneling speed classification for next generation multi-bit/cell NAND FLASH

2012 Symposium on VLSI Circuits (VLSIC) ◽

10.1109/vlsic.2012.6243827 ◽

2012 ◽

Author(s):

Yong Sung Cho ◽

Il Han Park ◽

Sang Young Yoon ◽

Nam Hee Lee ◽

Sang Hyun Joo ◽

...

Keyword(s):

Program Scheme ◽

Next Generation

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A 2.8GS/s 44.6mW time-interleaved ADC achieving 50.9dB SNDR and 3dB effective resolution bandwidth of 1.5GHz in 65nm CMOS

2012 Symposium on VLSI Circuits (VLSIC) ◽

10.1109/vlsic.2012.6243801 ◽

2012 ◽

Author(s):

Dusan Stepanovic ◽

Borivoje Nikolic

Keyword(s):

Interleaved Adc ◽

Time Interleaved ◽

Resolution Bandwidth

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A 4320p 60fps H.264/AVC intra-frame encoder chip with 1.41Gbins/s CABAC

2012 Symposium on VLSI Circuits (VLSIC) ◽

10.1109/vlsic.2012.6243836 ◽

2012 ◽

Author(s):

Dajiang Zhou ◽

Gang He ◽

Wei Fei ◽

Zhixiang Chen ◽

Jinjia Zhou ◽

...

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A 900mA 93% efficient 50µA quiescent current fixed frequency hysteretic buck converter using a highly digital hybrid voltage- and current-mode control

2012 Symposium on VLSI Circuits (VLSIC) ◽

10.1109/vlsic.2012.6243850 ◽

2012 ◽

Author(s):

Qadeer Khan ◽

Amr Elshazly ◽

Sachin Rao ◽

Rajesh Inti ◽

Pavan Kumar Hanumolu

Keyword(s):

Current Mode ◽

Buck Converter ◽

Fixed Frequency ◽

Current Mode Control ◽

Mode Control ◽

Quiescent Current

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Design of a 2.5-GHz, 3-ps jitter, 8-locking-cycle, all-digital delay-locked loop with cycle-by-cycle phase adjustment

2012 Symposium on VLSI Circuits (VLSIC) ◽

10.1109/vlsic.2012.6243852 ◽

2012 ◽

Author(s):

Chun-Yuan Cheng ◽

Jinn-Shyan Wang ◽

Cheng-Tai Yeh ◽

Jenn-Shyan Sheu

Keyword(s):

Cycle Phase ◽

Delay Locked Loop ◽

Phase Adjustment

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A 28nm high-k metal-gate SRAM with Asynchronous Cross-Couple Read Assist (AC2RA) circuitry achieving 3x reduction on speed variation for single ended arrays

2012 Symposium on VLSI Circuits (VLSIC) ◽

10.1109/vlsic.2012.6243791 ◽

2012 ◽

Author(s):

Robin Lee ◽

Jung-Ping Yang ◽

Chia-En Huang ◽

Chih-Chieh Chiu ◽

Wei-Shuo Kao ◽

...

Keyword(s):

Speed Variation ◽

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A 10 MHz BW 50 fJ/conv. continuous time ΔΣ modulator with high-order single opamp integrator using optimization-based design method

2012 Symposium on VLSI Circuits (VLSIC) ◽

10.1109/vlsic.2012.6243839 ◽

2012 ◽

Author(s):

Kazuo Matsukawa ◽

Koji Obata ◽

Yosuke Mitani ◽

Shiro Dosho

Keyword(s):

Continuous Time ◽

Design Method ◽

Optimization Based Design

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