Interface Engineering in the High-k Dielectric Gate Stacks

Author(s):  
Shijie Wang ◽  
Yuanping Feng ◽  
Alfred C. H. Huan
2008 ◽  
Vol 85 (1) ◽  
pp. 61-64 ◽  
Author(s):  
F.T. Docherty ◽  
M. MacKenzie ◽  
A.J. Craven ◽  
D.W. McComb ◽  
S. De Gendt ◽  
...  
Keyword(s):  
High K ◽  

2007 ◽  
Vol 84 (9-10) ◽  
pp. 2032-2034 ◽  
Author(s):  
A.A. Demkov ◽  
O. Sharia ◽  
J.K. Lee

2009 ◽  
Vol 86 (3) ◽  
pp. 214-217 ◽  
Author(s):  
P. Longo ◽  
A.J. Craven ◽  
M.C. Holland ◽  
D.A.J. Moran ◽  
I.G. Thayne
Keyword(s):  
High K ◽  

2001 ◽  
Vol 76-77 ◽  
pp. 19-22 ◽  
Author(s):  
J.J. Guan ◽  
Glenn W. Gale ◽  
G. Bersuker ◽  
M. Jackson ◽  
Howard R. Huff

Author(s):  
Alexander A. Demkov ◽  
Xuhui Luo ◽  
Onise Sharia
Keyword(s):  
High K ◽  

2016 ◽  
Vol 709 ◽  
pp. 19-22 ◽  
Author(s):  
Fatimah A. Noor ◽  
Christoforus Bimo ◽  
Khairurrijal

In this paper, we present a model of gate tunneling current in cylindrical surrounding-gate MOSFETs through dual layer high-k dielectric/SiO2 stacks. The model was derived under a quantum perturbation theory by taking into account both structural and electrical confinement effects. The influences of high-k materials and SiO2 thickness on the gate tunneling current have been studied. The calculated results show that the HfO2 is the most effective high-k material to decrease the gate tunneling current. It is also shown that the gate tunneling current is reduced with the SiO2 thickness. In addition, the obtained tunneling currents are fitted well with those obtained under the self-consistent calculation.


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