Simulation of the characteristics of low-voltage gates on combined cylindrical surrounding gate field-effect nanotransistors

The applicability of the architecture of a nanoscale surrounding gate field-effect transistor with a combined cylindrical working area for low-voltage applications is discussed. At the same time, the licensed TCAD Sentaurus instrument and technological modeling system is used as a tool. The transistor architecture under consideration involves combining the working zones of n-channel and p-channel transistors with one common gate. At the same time, the efficiency of suppressing short-channel effects is maintained and a high level of transistor current is provided in the strong inversion mode. Based on this architecture, a TCAD model of the NAND gate has been developed, the design of which contains two independent surrounding gates one combined working area. The use of the proposed gate architecture makes it possible to reduce the number of required transistor structures per gate by three times. This leads to a decrease in the switched capacity and power dissipation. From the simulation results, the gate geometric parameters with a working area length of 25 nm and a diameter of 8.5 nm, which can function at control voltages of 0.5 V in the frequency range up to 20 GHz with high gain, are determined. The switching time delay is 0.81 ps. The TCAD model of a half-adder is developed in the basis 2NAND. According to the simulation results, the efficiency of the prototype, which performs binary code addition operations with a delay of 4.2 ps at a supply voltage of 0.5 V and a frequency of 20 GHz, is shown. The obtained results create a theoretical basis for the synthesis of low-voltage complex functional blocks with high performance and minimal occupied area, which meets modern requirements for digital applications.

Analytical Drain-Current Model and Surface-Potential Calculation for Junctionless Cylindrical Surrounding-Gate MOSFETs

In this paper, we propose an analytical drain-current model for long-channel junctionless (JL) cylindrical surrounding-gate MOSFET (SRG MOSFET). It is based on surface-potential solutions obtained from Poisson’s equation using some approximations and separate conditions. Furthermore, analytical compact expressions of the drain-current have been derived for deep depletion, partial depletion, and accumulation mode. The confrontation of the model with TCAD simulation results, performed with Silvaco Software, proves the validity and the accuracy of the developed model