Energy‐efficient system‐on‐chip reconfigurable architecture design for sum of absolute difference computation in motion estimation process of H.265/HEVC video encoding

2019 ◽  
Author(s):  
K.R. Sarath Chandran ◽  
Premanand Venkatesh Chandramani
Keyword(s):  
Motion Estimation ◽  
Energy Efficient ◽  
System On Chip ◽  
Video Encoding ◽  
Reconfigurable Architecture ◽  
Absolute Difference ◽  
Architecture Design ◽  
Efficient System ◽  
Estimation Process ◽  
On Chip

scholarly journals A Heterogeneous Multicore System on Chip for Energy Efficient Brain Inspired Computing

2018 ◽  
Vol 65 (8) ◽  
pp. 1094-1098 ◽  
Author(s):  
Antonio Pullini ◽  
Francesco Conti ◽  
Davide Rossi ◽  
Igor Loi ◽  
Michael Gautschi ◽  
...  
Keyword(s):  
Energy Efficient ◽  
System On Chip ◽  
Heterogeneous Multicore ◽  
Multicore System ◽  
On Chip

Reliable and efficient system-on-chip design

Computer ◽  
2004 ◽  
Vol 37 (3) ◽  
pp. 42-50 ◽  
Author(s):  
N.R. Shanbhag
Keyword(s):  
System On Chip ◽  
Chip Design ◽  
Efficient System ◽  
On Chip

scholarly journals High Speed Parallel SAD Architecture Implementation on FPGA for HEVC encoder

2019 ◽  
Vol 8 (6) ◽  
pp. 1235-1238
Keyword(s):  
Motion Estimation ◽  
Video Compression ◽  
High Speed ◽  
High Performance ◽  
High Efficiency ◽  
Block Size ◽  
Video Encoding ◽  
Computational Time ◽  
Absolute Difference ◽  
Asymmetric Mode

Video compression is a very complex and time consuming task which generally pursuit high performance. Motion Estimation (ME) process in any video encoder is responsible to primarily achieve the colossal performance which contributes to significant compression gain. Summation of Absolute Difference (SAD) is widely applied as distortion metric for ME process. With the increase in block size to 64×64 for real time applications along with the introduction of asymmetric mode motion partitioning(AMP) in High Efficiency Video Encoding (HEVC)causes variable block size motion estimation very convoluted. This results in increase in computational time and demands for significant requirement of hardware resources. In this paper parallel SAD hardware circuit for ME process in HEVC is propound where parallelism is used at various levels. The propound circuit has been implemented using Xilinx Virtex-5 FPGA for XC5VLX20T family. Synthesis results shows that the propound circuit provides significant reduction in delay and increase in frequency in comparison with results of other parallel architectures.

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