scholarly journals Iterative Decoding of LDPC-Based Product Codes and FPGA-Based Performance Evaluation

Electronics ◽  
2020 ◽  
Vol 9 (1) ◽  
pp. 122
Author(s):  
Weigang Chen ◽  
Wenting Zhao ◽  
Hui Li ◽  
Suolei Dai ◽  
Changcai Han ◽  
...  
Keyword(s):  
Bit Error Rate ◽  
Error Rate ◽  
Iterative Decoding ◽  
Ldpc Codes ◽  
Low Complexity ◽  
High Rate ◽  
Error Floor ◽  
Product Codes ◽  
Field Programmable ◽  
Implementation Costs

Low-density parity-check (LDPC) codes have the potential for applications in future high throughput optical communications due to their significant error correction capability and the parallel decoding. However, they are not able to satisfy the very low bit error rate (BER) requirement due to the error floor phenomenon. In this paper, we propose a low-complexity iterative decoding scheme for product codes consisting of very high rate outer codes and LDPC codes. The outer codes aim at eliminating the residual error floor of LDPC codes with quite low implementation costs. Furthermore, considering the long simulation time of computer simulation for evaluating very low BER, the hardware platform is built to accelerate the evaluation of the proposed iterative decoding methods. Simultaneously, the fixed-point effects of the decoding algorithms are also be evaluated. The experimental results show that the iterative decoding of the product codes can achieve a quite low bit error rate. The evaluation using field programmable gate array (FPGA) also proves that product codes with LDPC codes and high-rate algebraic codes can achieve a good trade-off between complexity and throughput.

An Effective Low-Complexity Error-Floor Lowering Technique for High-Rate QC-LDPC Codes

2018 ◽  
Vol 22 (10) ◽  
pp. 1988-1991 ◽  
Author(s):  
Huang-Chang Lee ◽  
Po-Chiao Chou ◽  
Yeong-Luh Ueng
Keyword(s):  
Ldpc Codes ◽  
Low Complexity ◽  
High Rate ◽  
Error Floor

scholarly journals Performances of BICM-ID system using CRSC code in optical transmissions

2020 ◽  
Vol 0 (0) ◽  
Author(s):  
Hocine Fekih ◽  
Boubakar Seddik Bouazza ◽  
Keltoum Nouri
Keyword(s):  
Bit Error Rate ◽  
Error Rate ◽  
Iterative Decoding ◽  
Optical Transmission ◽  
Coded Modulation ◽  
Modulation Scheme ◽  
Coding Gain ◽  
Decoding Algorithms ◽  
Qam Modulation ◽  
Short Code

AbstractRecently, using iterative decoding algorithms to achieve an interesting bit error rate for spectrally efficient modulation become a necessity for optical transmission, in this paper, we propose a coded modulation scheme based on bit interleaving circular recursive systematic convolutional (CRSC) code and 16-QAM modulation. The proposal system considered as a serial concatenation of a channel encoder, a bit interleaver and M-ary modulator can be flexible easy to implement using a short code length. For a spectral efficiency $\eta =3\text{bit}/s/Hz$, the coding gain at a bit error rate of 10−6 is about 8 dB.

Low-complexity high-rate irregular QC-LDPC codes with applications to PR2 and EPR2 channels

2012 ◽  
Vol 25 (3) ◽  
pp. 370-382
Author(s):  
Virasit Imtawil ◽  
Mongkol Kupimai ◽  
Anan Kruesubthaworn ◽  
Apirat Siritaratiwat ◽  
Anupap Meesomboon
Keyword(s):  
Ldpc Codes ◽  
Low Complexity ◽  
High Rate

scholarly journals Nonlinear Product Codes and Their Low Complexity Iterative Decoding

ETRI Journal ◽  
2010 ◽  
Vol 32 (4) ◽  
pp. 588-595 ◽  
Author(s):  
Haesik Kim ◽  
Garik Markarian ◽  
Valdemar C. da Rocha, Jr.
Keyword(s):  
Iterative Decoding ◽  
Low Complexity ◽  
Product Codes

Hamming Product Code Based Multiple Bit Error Correction Coding Scheme Using Keyboard Scan Based Decoding for on Chip Interconnects Links

2012 ◽  
Vol 241-244 ◽  
pp. 2457-2461 ◽  
Author(s):  
Murali Maheswari ◽  
Gopalakrishnan Seetharaman
Keyword(s):  
Error Correction ◽  
Error Rate ◽  
Iterative Decoding ◽  
Error Control ◽  
Low Complexity ◽  
Hardware Complexity ◽  
Error Correction Coding ◽  
Product Code ◽  
Coding Scheme ◽  
On Chip

In this paper, we present multiple bit error correction coding scheme using extended Hamming product code combined with type II HARQ and keyboard scan based error flipping to correct multiple bit errors for on chip interconnect. The keyboard scan based error flipping reduces the hardware complexity of the decoder compared to the existing three stages iterative decoding method for on chip interconnects. The proposed method of decoding achieves 86% of reduction in area and 23% of reduction in decoder delay with only small increase in residual flit error rate compared to the existing three stage iterative decoding scheme for multiple bit error correction. The proposed code also achieves excellent improvement in residual flit error rate and up to 66% of links power consumption compared to the other error control schemes. The low complexity and excellent residual flit error rate make the proposed code suitable for on chip interconnection links.

A Novel Construction Method of QC-LDPC Codes Based on Generalized ACE Constrained

2013 ◽  
Vol 760-762 ◽  
pp. 1684-1689
Author(s):  
Hong Hao Zhao ◽  
Fan Bo Meng ◽  
Qing Qi Zhao ◽  
Jie Wang
Keyword(s):  
Computational Complexity ◽  
Bit Error Rate ◽  
Error Rate ◽  
Ldpc Codes ◽  
Excellent Performance ◽  
Frame Error Rate ◽  
Signal Noise ◽  
Extrinsic Message Degree ◽  
Lower Complexity ◽  
Simulation Results

Recently, structured LDPC codes have been focused on due to excellent performance and lower complexity. An improved construction of QC-LDPC based on a modified PEG algorithm is proposed in this paper. The modified Progressive Edge-Growth algorithm is a PEG algorithm with Approximated Cycle Extrinsic Message Degree (ACE) metric, which is used to describe the connectivity of cycles. The approach can maximize the girth of the cycles, improve the connectivity of cycles and have the advantages of QC algorithms. The simulation results demonstrate that the PEG algorithm based on ACE has lower Bit Error Rate (BER) and Frame Error Rate (FER) than the original PEG algorithm at the low Signal Noise Ratio (SNR) values, and has a relatively lower computational complexity.

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