Reconfigurable Modular Arithmetic Logic Unit for High-Performance Public-Key Cryptosystems

2006 ◽  
pp. 347-357 ◽  
Author(s):  
K. Sakiyama ◽  
N. Mentens ◽  
L. Batina ◽  
B. Preneel ◽  
I. Verbauwhede
Keyword(s):  
High Performance ◽  
Public Key ◽  
Modular Arithmetic ◽  
Public Key Cryptosystems ◽  
Arithmetic Logic Unit ◽  
Logic Unit

scholarly journals Reconfigurable modular arithmetic logic unit supporting high-performance RSA and ECC over GF(p)

2007 ◽  
Vol 94 (5) ◽  
pp. 501-514 ◽  
Author(s):  
K. Sakiyama ◽  
N. Mentens ◽  
L. Batina ◽  
B. Preneel ◽  
I. Verbauwhede
Keyword(s):  
High Performance ◽  
Modular Arithmetic ◽  
Arithmetic Logic Unit ◽  
Logic Unit

scholarly journals Estimation of Various Scalar Multiplication Algorithms in ECC

2019 ◽  
Vol 8 (6S4) ◽  
pp. 183-186
Keyword(s):  
High Performance ◽  
Additive Group ◽  
Public Key Cryptography ◽  
Scalar Multiplication ◽  
Public Key ◽  
Integer Multiple ◽  
Public Key Cryptosystems ◽  
Fast Processing ◽  
Implementation Costs ◽  
Modern Era

this modern era of security, public key cryptography is quite popular and holds a great significance. Various public key cryptosystems are available in today’s environment such as RSA and ECC. Elliptic Curve cryptography is beneficial in a lot of aspects which includes shorter key as compared to other cryptosystems, high security, fast processing speed, low storage, low bandwidth, small software print, low hardware implementation costs, high performance. The main and the costliest step in ECC is the Scalar Multiplication. In scalar multiplication, integer multiple of an element in additive group of elliptic curves is calculated. In this paper, we compare various available algorithms for the scalar multiplication used in ECC.

scholarly journals Design Methodology of a 32-bit Arithmetic Logic Unit with an Adaptive Leaf-cell Based Layout Technique

VLSI Design ◽  
2002 ◽  
Vol 14 (3) ◽  
pp. 249-258 ◽  
Author(s):  
Kiseon Cho ◽  
Minkyu Song
Keyword(s):  
High Performance ◽  
Design Methodology ◽  
Experimental Results ◽  
Cmos Process ◽  
Leaf Cell ◽  
Arithmetic Logic Unit ◽  
Barrel Shifter ◽  
Layout Technique ◽  
Logic Unit

In general, an arithmetic logic unit (ALU) of a DSP core is composed of an adder, multiplier and shifter. In order to obtain a high-performance 32-bit ALU, in this paper, an adaptive leaf-cell based layout technique is proposed. Thus novel architectures of 64-bit adder, 32 × 32-bit multiplier, and 32-bit shifter are proposed. The architecture of the proposed 64-bit adder is based on the conditional select addition with regular adaptive multiplexers. Secondly, novel optimized data compressors with a compound logic are proposed in a 32 × 32-bit multiplier. Finally, a shift algorithm with a pre-mask decoder is proposed for the 32-bit barrel shifter. They have been fabricated with 0.25 μm 1-poly 5-metal CMOS process, and we have obtained desired experimental results.

Comparative Analysis of CNTFET and CMOS Logic based Arithmetic Logic Unit

2017 ◽  
Vol 9 (4) ◽  
pp. 04018-1-04018-4
Author(s):  
K. Nehru ◽  
◽  
T. Nagarjuna ◽  
G. Vijay ◽  
◽  
...  
Keyword(s):  
Comparative Analysis ◽  
Arithmetic Logic Unit ◽  
Logic Unit
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