Design of a 40 GHz low noise amplifier using multigate technique for cascode devices

Increased parasitic components in silicon-based nanometer (nm) scale active devices have various performance trade-offs between optimizing the key parameters, for example, maximum frequency of oscillation ($$f_{max}$$ f max , gate resistance and capacitance, etc. A common-source cascode device is commonly used in amplifier designs at RF/millimeter-wave (mmWave) frequencies. In addition to intrinsic parasitic components, extrinsic components due to wiring and layout effects, are also critical for performance and accurate modelling of the devices. In this work, a comparison of two different layout techniques for cascode devices is presented to optimize the extrinsic parasitic elements, such as gate resistance. A multi-gate or multi-port layout technique is proposed for optimizing the gate resistance ($$r_g$$ r g ). Extracted values from measurement results show reduction of 10% in $$r_{g}$$ r g of multi-gate layout technique compared to a conventional gate-above-device layout for cascode devices. However, conventional layout exhibits smaller gate-to-source and gate-to-drain capacitances which leads to better performance in terms of speed, i.e. $$f_{max}$$ f max . An LNA is designed at 40 GHz frequency using proposed multi-gate cascode device. LNA achieves a measured peak gain of 10.2 dB and noise figure of 4.2 dB at 40 GHz. All the structures are designed and fabricated using 45 nm CMOS silicon on insulator (SOI) technology.

Inscribing God’s Word

Since the first century of Islam, Muslims have inscribed Qur’anic verses and phrases on buildings and other objects made for a wide range of purposes. This chapter addresses these inscriptions. An introductory section lays out the scope and limitations, the historiography of the subject, and some of the directions research has taken and might take. A second section surveys the ways that these Qur’anic texts have been used, showing both how Muslims considered the Revelation and how they cited it. A third section deals with layout, technique, and style, investigating how these formal features enhanced the message. Along the way, the chapter also points out directions in which such Qur’anic inscriptions might be profitably studied in these and other ways.

CerebroVis: Designing an Abstract yet Spatially Contextualized Cerebral Artery Network Visualization

Blood circulation in the human brain is supplied through a network of cerebral arteries. If a clinician suspects a patient has a stroke or other cerebrovascular condition, they order imaging tests. Neuroradiologists visually search the resulting scans for abnormalities. Their visual search tasks correspond to the abstract network analysis tasks of browsing and path following. To assist neuroradiologists in identifying cerebral artery abnormalities, we designed CerebroVis, a novel abstract-yet spatially contextualized-cerebral artery network visualization. In this design study, we contribute a novel framing and definition of the cerebral artery system in terms of network theory and characterize neuroradiologist domain goals as abstract visualization and network analysis tasks. Through an iterative, user-centered design process we developed an abstract network layout technique which incorporates cerebral artery spatial context. The abstract visualization enables increased domain task performance over 3D geometry representations, while including spatial context helps preserve the user's mental map of the underlying geometry. We provide open source implementations of our network layout technique and prototype cerebral artery visualization tool. We demonstrate the robustness of our technique by successfully laying out 61 open source brain scans. We evaluate the effectiveness of our layout through a mixed methods study with three neuroradiologists. In a formative controlled experiment our study participants used CerebroVis and a conventional 3D visualization to examine real cerebral artery imaging data to identify a simulated intracranial artery stenosis. Participants were more accurate at identifying stenoses using CerebroVis (absolute risk difference 13%). A free copy of this paper, the evaluation stimuli and data, and source code are available at osf.io/e5sxt.

A Layout Technique To Reduce The Impact Of Parasitic Capacitors Within A Capacitor Array On The Nonlinearity Of Data Converters.

SAR ADC has a moderate speed, Low area and low cost compared to other ADC implementations. The accuracy expected from a commercial SAR ADC is very high and research has been going on for many years to improve the accuracy. The Linearity of the data converters is the key for accuracy. The Integral nonlinearity and differential nonlinearity errors of data converters are governed by the matching of the unit capacitors/resistors with in capacitor/resistor array. Layout of these arrays can add significant parasitics affecting the nonlinearity of data converters. This paper presents a layout technique to reduce the impact of the parastics on data converter’s nonlinearity.